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剪除tilelink接口，直接用mem

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This commit is contained in:
RuigeLee
2024-11-01 14:53:52 +08:00
parent b13a3b8aad
commit db5fe252d7
6 changed files with 268 additions and 162 deletions
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74
src/main/scala/backBoard/pico/TLCDR.scala
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@@ -8,7 +8,7 @@ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule {
abstract class TLCDRBase()(implicit p: Parameters) extends BackModule {
class TLCDRIO extends Bundle{
val overCLK = Input(Bool())
val dDatIn = Input(Bool())
@@ -16,8 +16,7 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac
val uDatIn = Input(Bool())
val uDatOut = Output(Bool())
val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
val tld = new DecoupledIO(new TLBundleD(edge.bundle))
val mem = Flipped(new Mem_Port_Bundle)
val interrupt = Output(Vec(4, Bool()))
}
@@ -35,9 +34,6 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac
io.uDatOut := dirSel & CDROut.io.serDat
// CDRIn.io.axis = Decoupled(new AXIS_Bundle(8))
// CDROut.io.axis = Flipped(Decoupled(new AXIS_Bundle(8)))
val txFifo = Module(new Queue(UInt(32.W), 4))
val rxFifo = Module(new Queue(UInt(32.W), 4))
@@ -47,9 +43,9 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac
trait TLCDRTx{ this: TLCDRBase =>
val isTLReadStatus = io.tla.fire & io.tla.bits.address(4,0) === "h0".U & ( io.tla.bits.opcode === 4.U )
val isTLWriteTxLen = io.tla.fire & io.tla.bits.address(4,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLWriteTxFifo = io.tla.fire & io.tla.bits.address(4,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isTLReadStatus = io.mem.fire & io.mem.addr(4,0) === "h0".U & ( io.mem.wstrb === 0.U )
val isTLWriteTxLen = io.mem.fire & io.mem.addr(4,0) === "h4".U & ( io.mem.wstrb =/= 0.U )
val isTLWriteTxFifo = io.mem.fire & io.mem.addr(4,0) === "h8".U & ( io.mem.wstrb =/= 0.U )
val txLen = RegInit(0.U(12.W))
@@ -108,12 +104,12 @@ trait TLCDRTx{ this: TLCDRBase =>
when( isTLWriteTxLen ){
txLen := io.tla.bits.data
txLen := io.mem.wdata
} .elsewhen( CDROut.io.axis.fire ){
txLen := txLen - 1.U
}
txFifo.io.enq.bits := io.tla.bits.data
txFifo.io.enq.bits := io.mem.wdata
txFifo.io.enq.valid := isTLWriteTxFifo & txLen =/= 0.U
when( isTLWriteTxLen ){
@@ -131,10 +127,10 @@ trait TLCDRTx{ this: TLCDRBase =>
trait TLCDRRx{ this: TLCDRBase =>
val isTLWriteSoftReset = io.tla.fire & io.tla.bits.address(4,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
// val isTLReadRxStatus = io.tla.fire & io.tla.bits.address(4,0) === "h14".U & ( io.tla.bits.opcode === 4.U )
val isTLReadRxLen = io.tla.fire & io.tla.bits.address(4,0) === "h18".U & ( io.tla.bits.opcode === 4.U )
val isTLReadRxFifo = io.tla.fire & io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U )
val isTLWriteSoftReset = io.mem.fire & io.mem.addr(4,0) === "h10".U & ( (io.mem.wstrb =/= 0.U) )
// val isTLReadRxStatus = io.mem.fire & io.mem.addr(4,0) === "h14".U & ( io.mem.wstrb === 0.U )
val isTLReadRxLen = io.mem.fire & io.mem.addr(4,0) === "h18".U & ( io.mem.wstrb === 0.U )
val isTLReadRxFifo = io.mem.fire & io.mem.addr(4,0) === "h1c".U & ( io.mem.wstrb === 0.U )
val rxLen = RegInit(0.U(12.W))
// val isRxBusy = RegInit(false.B)
@@ -209,24 +205,23 @@ trait TLCDRRx{ this: TLCDRBase =>
}
class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with TLCDRTx with TLCDRRx{
class TLCDR()(implicit p: Parameters) extends TLCDRBase() with TLCDRTx with TLCDRRx{
val isWriteTransDir = io.mem.fire & io.mem.addr(4,0) === "hc".U & io.mem.wstrb =/= 0.U
val isWriteTransDir = io.tla.fire & io.tla.bits.address(4,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val tlaInfo = Reg(new TLBundleA(edge.bundle))
val rdata = Reg(UInt(32.W))
val tlAReady = RegInit(true.B)
val tlDValid = RegInit(false.B)
val isRead = tlaInfo.opcode === 4.U
when( isWriteTransDir ){
dirSel := io.tla.bits.data
dirSel := io.mem.wdata
}
io.mem.ready :=
( io.mem.wstrb =/= 0.U & txFifo.io.enq.ready) |
( io.mem.wstrb === 0.U & Mux( io.mem.addr(4,0) === "h1c".U, rxFifo.io.deq.valid, true.B ) )
io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) )
io.tld.valid := tlDValid
io.interrupt(0) := intTxError
io.interrupt(1) := intRxError
@@ -234,32 +229,15 @@ class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with
io.interrupt(3) := intRxEnd
when( io.tla.fire ) {
tlaInfo := io.tla.bits
}
io.mem.rdata :=
Mux1H(Seq(
isTLReadStatus -> Cat( isRxValid, isRxError, isTxBusy, isTxFull, isTxError),
isTLReadRxLen -> rxLen,
isTLReadRxFifo -> rxFifo.io.deq.bits
))
when( io.tla.fire ){
tlAReady := false.B
tlDValid := true.B
} .elsewhen( io.tld.fire ) {
tlAReady := true.B
tlDValid := false.B
}
when(isRead) {
io.tld.bits := edge.AccessAck(tlaInfo, rdata)
} .otherwise {
io.tld.bits := edge.AccessAck(tlaInfo)
}
when( isTLReadStatus){
rdata := Cat( isRxValid, isRxError, isTxBusy, isTxFull, isTxError )
} .elsewhen(isTLReadRxLen ){
rdata := rxLen
} .elsewhen(isTLReadRxFifo ){
rdata := rxFifo.io.deq.bits
}
}