ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

剪除tilelink接口，直接用mem

Browse Source
This commit is contained in:
RuigeLee
2024-11-01 14:53:52 +08:00
parent b13a3b8aad
commit db5fe252d7
6 changed files with 268 additions and 162 deletions
Download Patch File Download Diff File Expand all files Collapse all files

41
src/main/scala/backBoard/pico/SimpleGpio.scala
View File

@@ -8,10 +8,9 @@ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
class SimpleGpio(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule{
class SimpleGpio()(implicit p: Parameters) extends BackModule{
class SimpleGpioIO extends Bundle{
val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
val tld = new DecoupledIO(new TLBundleD(edge.bundle))
val mem = Flipped(new Mem_Port_Bundle)
val out = Output(UInt(32.W))
val in = Input(UInt(32.W))
@@ -24,36 +23,20 @@ class SimpleGpio(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule{
val io: SimpleGpioIO = IO(new SimpleGpioIO)
val isWriteGpio = io.tla.fire & io.tla.bits.address(6,0) === "h0".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isReadGpio = io.tla.fire & io.tla.bits.address(3,0) === "h0".U & ( io.tla.bits.opcode === 4.U )
// val isWriteDir = io.tla.fire & io.tla.bits.address(6,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
val isReadIsLast = io.tla.fire & io.tla.bits.address(3,0) === "h8".U & ( io.tla.bits.opcode === 4.U )
val isWriteGpio = io.mem.fire & io.mem.addr(3,0) === "h0".U & io.mem.wstrb =/= 0.U
val isReadGpio = io.mem.fire & io.mem.addr(3,0) === "h0".U & io.mem.wstrb === 0.U
// val isWriteDir = io.mem.fire & io.mem.addr(3,0) === "h4".U & io.mem.wstrb =/= 0.U
val isReadIsLast = io.mem.fire & io.mem.addr(3,0) === "h8".U & io.mem.wstrb === 0.U
io.isOnline := false.B
val tldValid = RegInit(false.B)
val tlaInfo = Reg(new TLBundleA(edge.bundle))
val isRead = Reg(Bool())
io.out := RegEnable( io.mem.wdata, 0.U(32.W), isWriteGpio )
io.out := RegEnable( io.tla.bits.data, 0.U(32.W), isWriteGpio )
io.mem.ready := true.B
io.mem.rdata :=
Mux( io.mem.addr(3,0) === "h0".U, io.in,
Mux( io.mem.addr(3,0) === "h8".U, io.isLast, 0.U ) )
when( io.tld.fire ){
tldValid := false.B
} .elsewhen( io.tla.fire ){
tldValid := true.B
tlaInfo := io.tla.bits
isRead := io.tla.bits.opcode === 4.U
}
}
io.tla.ready := true.B
io.tld.valid := tldValid
when(isRead) {
io.tld.bits := edge.AccessAck(tlaInfo,
Mux( tlaInfo.address(3,0) === "h0".U, io.in, Mux( tlaInfo.address(3,0) === "h8".U, io.isLast, 0.U ) )
)
} .otherwise {
io.tld.bits := edge.AccessAck(tlaInfo)
}
}