剪除tilelink接口，直接用mem

2024-11-01 14:53:52 +08:00
parent b13a3b8aad
commit db5fe252d7
6 changed files with 268 additions and 162 deletions
--- a/src/main/resources/picorv32.v
+++ b/src/main/resources/picorv32.v
@@ -59,7 +59,7 @@

 module picorv32 #(
 	parameter [ 0:0] ENABLE_COUNTERS = 1,
-	parameter [ 0:0] ENABLE_COUNTERS64 = 1,
+	parameter [ 0:0] ENABLE_COUNTERS64 = 0,
 	parameter [ 0:0] ENABLE_REGS_16_31 = 1,
 	parameter [ 0:0] ENABLE_REGS_DUALPORT = 1,
 	parameter [ 0:0] LATCHED_MEM_RDATA = 0,
@@ -76,13 +76,13 @@ module picorv32 #(
 	parameter [ 0:0] ENABLE_DIV = 0,
 	parameter [ 0:0] ENABLE_IRQ = 1,
 	parameter [ 0:0] ENABLE_IRQ_QREGS = 0,
-	parameter [ 0:0] ENABLE_IRQ_TIMER = 1,
+	parameter [ 0:0] ENABLE_IRQ_TIMER = 0,
 	parameter [ 0:0] ENABLE_TRACE = 0,
 	parameter [ 0:0] REGS_INIT_ZERO = 0,
 	parameter [31:0] MASKED_IRQ = 32'h 0000_0000,
 	parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff,
-	parameter [31:0] PROGADDR_RESET = 32'h 8000_0000,
-	parameter [31:0] PROGADDR_IRQ = 32'h 8000_0800,
+	parameter [31:0] PROGADDR_RESET = 32'h 0000_0000,
+	parameter [31:0] PROGADDR_IRQ = 32'h 0000_0800,
 	parameter [31:0] STACKADDR = 32'h ffff_ffff
 ) (
 	input clk, resetn,
--- a/src/main/scala/backBoard/pico/BackSystem.scala
+++ b/src/main/scala/backBoard/pico/BackSystem.scala
@@ -46,61 +46,53 @@ class BackCfg extends Config((_, _, _) => {

 class BackSys()(implicit p: Parameters) extends LazyModule with HasBackParameters {

-  val coreClientNode = TLClientNode(Seq(TLMasterPortParameters.v1(
-    Seq(TLMasterParameters.v1(
-      name = "core",
-      sourceId = IdRange(0, 1),
-    ))
-  )))
+  // val coreClientNode = TLClientNode(Seq(TLMasterPortParameters.v1(
+  //   Seq(TLMasterParameters.v1(
+  //     name = "core",
+  //     sourceId = IdRange(0, 1),
+  //   ))
+  // )))

-  val sram = LazyModule(new TLRAM(
-    address = AddressSet(0x00000000L, 0xfffL),
-    cacheable = false,
-    executable = true,
-    atomics = false,
-    beatBytes = 4,
-    sramReg = false, // drive SRAM data output directly into a register => 1 cycle longer response
-  ))
+  // val sram = LazyModule(new TLRAM(
+  //   address = AddressSet(0x00000000L, 0xfffL),
+  //   cacheable = false,
+  //   executable = true,
+  //   atomics = false,
+  //   beatBytes = 4,
+  //   sramReg = false, // drive SRAM data output directly into a register => 1 cycle longer response
+  // ))

-  val cdrNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
-    managers = Seq(TLSlaveParameters.v1(
-      address = Seq(AddressSet(0x00001000L, 0xffL)),
-      regionType = RegionType.UNCACHED,
-      executable = false,
-      supportsGet         = TransferSizes(32/8, 32/8),
-      supportsPutFull     = TransferSizes(32/8, 32/8),
-      supportsPutPartial  = TransferSizes(32/8, 32/8)
-    )),
-    beatBytes = 32/8)))
+  // val cdrNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
+  //   managers = Seq(TLSlaveParameters.v1(
+  //     address = Seq(AddressSet(0x00001000L, 0xffL)),
+  //     regionType = RegionType.UNCACHED,
+  //     executable = false,
+  //     supportsGet         = TransferSizes(32/8, 32/8),
+  //     supportsPutFull     = TransferSizes(32/8, 32/8),
+  //     supportsPutPartial  = TransferSizes(32/8, 32/8)
+  //   )),
+  //   beatBytes = 32/8)))



+  // val gpioNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
+  //   managers = Seq(TLSlaveParameters.v1(
+  //     address = Seq(AddressSet(0x0002000L, 0xffL)),
+  //     regionType = RegionType.UNCACHED,
+  //     executable = false,
+  //     supportsGet         = TransferSizes(32/8, 32/8),
+  //     supportsPutFull     = TransferSizes(32/8, 32/8),
+  //     supportsPutPartial  = TransferSizes(32/8, 32/8)
+  //   )),
+  //   beatBytes = 32/8)))

-  // val uart = LazyModule( new TLUART(
-  //   busWidthBytes = 4,
-  //   params = UARTParams(
-  //     address = BigInt(0x50000000L),
-  //     initBaudRate = BigInt(115200),
-  //   ), divinit = 0) )
-
-  val gpioNode = TLManagerNode(Seq(TLSlavePortParameters.v1(
-    managers = Seq(TLSlaveParameters.v1(
-      address = Seq(AddressSet(0x0002000L, 0xffL)),
-      regionType = RegionType.UNCACHED,
-      executable = false,
-      supportsGet         = TransferSizes(32/8, 32/8),
-      supportsPutFull     = TransferSizes(32/8, 32/8),
-      supportsPutPartial  = TransferSizes(32/8, 32/8)
-    )),
-    beatBytes = 32/8)))
-
-  val xbar = TLXbar(
-    //policy = TLArbiter.lowestIndexFirst
-  )
-  xbar := coreClientNode
-  cdrNode := xbar
-  sram.node := xbar
-  gpioNode := xbar
+  // val xbar = TLXbar(
+  //   //policy = TLArbiter.lowestIndexFirst
+  // )
+  // xbar := coreClientNode
+  // cdrNode := xbar
+  // sram.node := xbar
+  // gpioNode := xbar



@@ -124,22 +116,22 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame
    val DCIn   = Input(Bool())
  }
  
-  val ( core_bus, core_edge ) = outer.coreClientNode.out.head
-  val ( cdr_bus, cdr_edge ) = outer.cdrNode.in.head
-  val ( gpio_bus, gpio_edge ) = outer.gpioNode.in.head
+  // val ( core_bus, core_edge ) = outer.coreClientNode.out.head
+  // val ( cdr_bus, cdr_edge ) = outer.cdrNode.in.head
+  // val ( gpio_bus, gpio_edge ) = outer.gpioNode.in.head


  val io: BackSysIO = IO(new BackSysIO)

-  val pico = Module(new Picorv32_tl(edge = core_edge))
-  val cdr = Module(new TLCDR(cdr_edge))
-
-  val gpio = Module(new SimpleGpio(gpio_edge))
+  val pico = Module(new Picorv32_mem )
+  // val pico = Module(new Picorv32_tl(edge = core_edge))
+  val cdr = Module(new TLCDR() )
+  val gpio = Module(new SimpleGpio() )
+  val sram = Module(new SimpleSRAM)


-    // val trap = Output(Bool())
  pico.io.irq := Cat( io.DCIn, cdr.io.interrupt.asUInt )
-    // val eoi = Output(UInt(32.W))
+

  io.out := gpio.io.out
  gpio.io.in := io.in
@@ -162,38 +154,73 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame



+  sram.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr(13,12) === "b00".U
+  cdr.io.mem.valid  := pico.io.mem.valid & pico.io.mem.addr(13,12) === "b01".U & ~pico.io.mem.instr
+  gpio.io.mem.valid := pico.io.mem.valid & pico.io.mem.addr(13,12) === "b10".U & ~pico.io.mem.instr
+
+  pico.io.mem.ready := 
+    Mux( pico.io.mem.instr, sram.io.mem.ready, 
+      Mux1H(Seq(
+        (pico.io.mem.addr(13,12) === "b00".U ) -> sram.io.mem.ready,
+        (pico.io.mem.addr(13,12) === "b01".U ) -> cdr.io.mem.ready,
+        (pico.io.mem.addr(13,12) === "b10".U ) -> gpio.io.mem.ready,
+      ))
+     )
+  pico.io.mem.rdata := 
+    Mux( pico.io.mem.instr, sram.io.mem.rdata,
+      Mux1H(Seq(
+        (pico.io.mem.addr(13,12) === "b00".U ) -> sram.io.mem.rdata,
+        (pico.io.mem.addr(13,12) === "b01".U ) ->  cdr.io.mem.rdata,
+        (pico.io.mem.addr(13,12) === "b10".U ) -> gpio.io.mem.rdata,
+      )) 
+    )
+
+  sram.io.mem.wdata := pico.io.mem.wdata
+   cdr.io.mem.wdata := pico.io.mem.wdata
+  gpio.io.mem.wdata := pico.io.mem.wdata
+
+  sram.io.mem.wstrb := pico.io.mem.wstrb
+   cdr.io.mem.wstrb := pico.io.mem.wstrb
+  gpio.io.mem.wstrb := pico.io.mem.wstrb
+
+  sram.io.mem.addr := pico.io.mem.addr(11,0)
+   cdr.io.mem.addr := pico.io.mem.addr(11,0)
+  gpio.io.mem.addr := pico.io.mem.addr(11,0)
+
+  sram.io.mem.instr := pico.io.mem.instr
+   cdr.io.mem.instr := false.B
+  gpio.io.mem.instr := false.B
+
+
+  assert( pico.io.mem.wstrb.andR | ~pico.io.mem.wstrb.orR )
+
+  // pico.io.tld.bits  := core_bus.d.bits
+  // pico.io.tld.valid := core_bus.d.valid
+  // core_bus.d.ready  := pico.io.tld.ready
+  // core_bus.a.valid  := pico.io.tla.valid
+  // core_bus.a.bits   := pico.io.tla.bits
+  // pico.io.tla.ready := core_bus.a.ready




-
-  pico.io.tld.bits  := core_bus.d.bits
-  pico.io.tld.valid := core_bus.d.valid
-  core_bus.d.ready  := pico.io.tld.ready
-  core_bus.a.valid  := pico.io.tla.valid
-  core_bus.a.bits   := pico.io.tla.bits
-  pico.io.tla.ready := core_bus.a.ready
+  // cdr.io.tla.valid := cdr_bus.a.valid & cdr_bus.a.bits.address(7) === "h0".U
+  // cdr.io.tla.bits  := cdr_bus.a.bits 
+  // cdr_bus.a.ready := cdr.io.tla.ready


+  // cdr_bus.d.valid := cdr.io.tld.valid
+  // cdr_bus.d.bits  := cdr.io.tld.bits  
+  // cdr.io.tld.ready  := cdr_bus.d.ready


-  cdr.io.tla.valid := cdr_bus.a.valid & cdr_bus.a.bits.address(7) === "h0".U
-  cdr.io.tla.bits  := cdr_bus.a.bits 
-  cdr_bus.a.ready := cdr.io.tla.ready
+  // gpio.io.tla.valid := gpio_bus.a.valid
+  // gpio.io.tla.bits  := gpio_bus.a.bits 
+  // gpio_bus.a.ready  := gpio.io.tla.ready

-
-  cdr_bus.d.valid := cdr.io.tld.valid
-  cdr_bus.d.bits  := cdr.io.tld.bits  
-  cdr.io.tld.ready  := cdr_bus.d.ready
-
-
-  gpio.io.tla.valid := gpio_bus.a.valid
-  gpio.io.tla.bits  := gpio_bus.a.bits 
-  gpio_bus.a.ready  := gpio.io.tla.ready
-
-  gpio_bus.d.valid  := gpio.io.tld.valid
-  gpio_bus.d.bits   := gpio.io.tld.bits
-  gpio.io.tld.ready := gpio_bus.d.ready
+  // gpio_bus.d.valid  := gpio.io.tld.valid
+  // gpio_bus.d.bits   := gpio.io.tld.bits
+  // gpio.io.tld.ready := gpio_bus.d.ready


 }
--- a/src/main/scala/backBoard/pico/Picorv32_mem.scala
+++ b/src/main/scala/backBoard/pico/Picorv32_mem.scala
@@ -0,0 +1,60 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+import org.chipsalliance.cde.config._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+
+class Mem_Port_Bundle extends Bundle{
+  val valid = Output(Bool())
+	val ready = Input(Bool())
+  val instr = Output(Bool())
+
+	val addr  = Output(UInt(32.W))
+	val wdata = Output(UInt(32.W))
+	val wstrb = Output(UInt(4.W))
+	val rdata = Input(UInt(32.W))
+
+  def fire = valid & ready
+}
+
+
+
+
+class Picorv32_mem()(implicit p: Parameters) extends BackModule{
+  class Picorv32IO_mem extends Bundle{
+
+    val mem = new Mem_Port_Bundle
+
+    val irq = Input(UInt(32.W))
+
+  }
+
+  val io: Picorv32IO_mem = IO(new Picorv32IO_mem)
+
+  val core = Module(new picorv32)
+
+	core.io.clk := clock.asBool
+  core.io.resetn := ~reset.asBool
+
+	core.io.pcpi_wr    := false.B
+	core.io.pcpi_rd    := 0.U
+	core.io.pcpi_wait  := false.B
+	core.io.pcpi_ready := true.B
+
+	core.io.irq := io.irq
+
+  io.mem.valid := core.io.mem_valid
+	core.io.mem_ready := io.mem.ready
+
+	io.mem.addr  := core.io.mem_addr
+	io.mem.wdata := core.io.mem_wdata
+	io.mem.wstrb := core.io.mem_wstrb
+  io.mem.instr := core.io.mem_instr
+	core.io.mem_rdata := io.mem.rdata
+}
+
+
+
--- a/src/main/scala/backBoard/pico/SimpleGpio.scala
+++ b/src/main/scala/backBoard/pico/SimpleGpio.scala
@@ -8,10 +8,9 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._


-class SimpleGpio(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule{
+class SimpleGpio()(implicit p: Parameters) extends BackModule{
  class SimpleGpioIO extends Bundle{
-    val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
-    val tld = new DecoupledIO(new TLBundleD(edge.bundle))
+    val mem = Flipped(new Mem_Port_Bundle)

    val out = Output(UInt(32.W))
    val in  = Input(UInt(32.W))
@@ -24,36 +23,20 @@ class SimpleGpio(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule{

  val io: SimpleGpioIO = IO(new SimpleGpioIO)

-  val isWriteGpio  = io.tla.fire & io.tla.bits.address(6,0) === "h0".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
-  val isReadGpio   = io.tla.fire & io.tla.bits.address(3,0) === "h0".U & ( io.tla.bits.opcode === 4.U )
-  // val isWriteDir   = io.tla.fire & io.tla.bits.address(6,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
-  val isReadIsLast = io.tla.fire & io.tla.bits.address(3,0) === "h8".U & ( io.tla.bits.opcode === 4.U )
+  val isWriteGpio  = io.mem.fire & io.mem.addr(3,0) === "h0".U & io.mem.wstrb =/= 0.U
+  val isReadGpio   = io.mem.fire & io.mem.addr(3,0) === "h0".U & io.mem.wstrb === 0.U
+  // val isWriteDir   = io.mem.fire & io.mem.addr(3,0) === "h4".U & io.mem.wstrb =/= 0.U
+  val isReadIsLast = io.mem.fire & io.mem.addr(3,0) === "h8".U & io.mem.wstrb === 0.U


  io.isOnline := false.B

-  val tldValid = RegInit(false.B)
-  val tlaInfo = Reg(new TLBundleA(edge.bundle))
-  val isRead = Reg(Bool())
+  io.out := RegEnable( io.mem.wdata, 0.U(32.W), isWriteGpio )

-  io.out := RegEnable( io.tla.bits.data, 0.U(32.W), isWriteGpio )
+  io.mem.ready := true.B
+  io.mem.rdata :=
+    Mux( io.mem.addr(3,0) === "h0".U, io.in, 
+      Mux( io.mem.addr(3,0) === "h8".U, io.isLast, 0.U ) )

-  when( io.tld.fire ){
-    tldValid := false.B
-  } .elsewhen( io.tla.fire ){
-    tldValid := true.B
-    tlaInfo := io.tla.bits
-    isRead := io.tla.bits.opcode === 4.U
-  }
+}

-  io.tla.ready := true.B
-  io.tld.valid := tldValid
-
-  when(isRead) {
-    io.tld.bits := edge.AccessAck(tlaInfo, 
-      Mux( tlaInfo.address(3,0) === "h0".U, io.in, Mux( tlaInfo.address(3,0) === "h8".U, io.isLast, 0.U ) )
-    )
-  } .otherwise {
-    io.tld.bits := edge.AccessAck(tlaInfo)
-  }
-}
--- a/src/main/scala/backBoard/pico/SimpleSRAM.scala
+++ b/src/main/scala/backBoard/pico/SimpleSRAM.scala
@@ -0,0 +1,58 @@
+package BACK
+
+import chisel3._
+import chisel3.util._
+
+import org.chipsalliance.cde.config._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+
+
+class SimpleSRAM()(implicit p: Parameters) extends BackModule{
+  class SimpleSRAMIO extends Bundle{
+    val mem = Flipped(new Mem_Port_Bundle)
+  }
+
+  val io: SimpleSRAMIO = IO(new SimpleSRAMIO)
+
+  val mem = SyncReadMem(1024, Vec(4, UInt(8.W)))
+
+
+  io.mem.rdata := DontCare
+
+  // when(io.mem.valid) {
+
+    mem.write(
+      io.mem.addr(11,2),
+      VecInit( io.mem.wdata(31,24), io.mem.wdata(23,16), io.mem.wdata(15,8), io.mem.wdata(7,0) ),
+      VecInit( io.mem.valid & io.mem.wstrb.extract(3), io.mem.valid & io.mem.wstrb.extract(2), io.mem.valid & io.mem.wstrb.extract(1), io.mem.valid & io.mem.wstrb.extract(0) )
+    )
+
+
+    io.mem.rdata := Cat( mem.read(io.mem.addr(11,2), true.B).reverse )
+
+
+
+    // when ( io.mem.wstrb =/= 0.U ) {
+    //   when(io.mem.wstrb.extract(0)) { mem(io.mem.addr(11,2))(0) := io.mem.wdata(7,0) }
+    //   when(io.mem.wstrb.extract(1)) { mem(io.mem.addr(11,2))(1) := io.mem.wdata(15,8) }
+    //   when(io.mem.wstrb.extract(2)) { mem(io.mem.addr(11,2))(2) := io.mem.wdata(23,16) }
+    //   when(io.mem.wstrb.extract(3)) { mem(io.mem.addr(11,2))(3) := io.mem.wdata(31,24) }
+    // } .otherwise { io.mem.rdata := Cat( mem(io.mem.addr(11,2)).reverse ) }
+  // }
+
+  val isReadAck = RegInit(false.B)
+  when( io.mem.fire ){
+    isReadAck := false.B
+  } .elsewhen( io.mem.valid & io.mem.wstrb === 0.U ){
+    isReadAck := true.B
+  }
+
+  io.mem.ready := 
+    ( io.mem.wstrb =/= 0.U & true.B    ) |
+    ( io.mem.wstrb === 0.U & isReadAck )
+
+
+
+
+}
--- a/src/main/scala/backBoard/pico/TLCDR.scala
+++ b/src/main/scala/backBoard/pico/TLCDR.scala
@@ -8,7 +8,7 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._


-abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends BackModule {
+abstract class TLCDRBase()(implicit p: Parameters) extends BackModule {
  class TLCDRIO extends Bundle{
    val overCLK = Input(Bool())
    val dDatIn   = Input(Bool())
@@ -16,8 +16,7 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac
    val uDatIn   = Input(Bool())
    val uDatOut  = Output(Bool())

-    val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
-    val tld = new DecoupledIO(new TLBundleD(edge.bundle))
+    val mem = Flipped(new Mem_Port_Bundle)

    val interrupt = Output(Vec(4, Bool()))
  }
@@ -35,9 +34,6 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac
  io.uDatOut :=  dirSel & CDROut.io.serDat


-  // CDRIn.io.axis = Decoupled(new AXIS_Bundle(8))
-  // CDROut.io.axis = Flipped(Decoupled(new AXIS_Bundle(8))) 
-

  val txFifo = Module(new Queue(UInt(32.W), 4))
  val rxFifo = Module(new Queue(UInt(32.W), 4))
@@ -47,9 +43,9 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac

 trait TLCDRTx{ this: TLCDRBase =>

-  val isTLReadStatus        = io.tla.fire & io.tla.bits.address(4,0) === "h0".U & ( io.tla.bits.opcode === 4.U )
-  val isTLWriteTxLen        = io.tla.fire & io.tla.bits.address(4,0) === "h4".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
-  val isTLWriteTxFifo       = io.tla.fire & io.tla.bits.address(4,0) === "h8".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
+  val isTLReadStatus        = io.mem.fire & io.mem.addr(4,0) === "h0".U & ( io.mem.wstrb === 0.U )
+  val isTLWriteTxLen        = io.mem.fire & io.mem.addr(4,0) === "h4".U & ( io.mem.wstrb =/= 0.U )
+  val isTLWriteTxFifo       = io.mem.fire & io.mem.addr(4,0) === "h8".U & ( io.mem.wstrb =/= 0.U )


  val txLen     = RegInit(0.U(12.W))
@@ -108,12 +104,12 @@ trait TLCDRTx{ this: TLCDRBase =>


  when( isTLWriteTxLen ){
-    txLen := io.tla.bits.data
+    txLen := io.mem.wdata
  } .elsewhen( CDROut.io.axis.fire ){
    txLen := txLen - 1.U
  }

-  txFifo.io.enq.bits  := io.tla.bits.data
+  txFifo.io.enq.bits  := io.mem.wdata
  txFifo.io.enq.valid := isTLWriteTxFifo & txLen =/= 0.U

  when( isTLWriteTxLen ){
@@ -131,10 +127,10 @@ trait TLCDRTx{ this: TLCDRBase =>

 trait TLCDRRx{ this: TLCDRBase => 

-  val isTLWriteSoftReset = io.tla.fire & io.tla.bits.address(4,0) === "h10".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )
-  // val isTLReadRxStatus     = io.tla.fire & io.tla.bits.address(4,0) === "h14".U & ( io.tla.bits.opcode === 4.U )
-  val isTLReadRxLen        = io.tla.fire & io.tla.bits.address(4,0) === "h18".U & ( io.tla.bits.opcode === 4.U )
-  val isTLReadRxFifo       = io.tla.fire & io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U )
+  val isTLWriteSoftReset = io.mem.fire & io.mem.addr(4,0) === "h10".U & ( (io.mem.wstrb =/= 0.U) )
+  // val isTLReadRxStatus     = io.mem.fire & io.mem.addr(4,0) === "h14".U & ( io.mem.wstrb === 0.U )
+  val isTLReadRxLen        = io.mem.fire & io.mem.addr(4,0) === "h18".U & ( io.mem.wstrb === 0.U )
+  val isTLReadRxFifo       = io.mem.fire & io.mem.addr(4,0) === "h1c".U & ( io.mem.wstrb === 0.U )

  val rxLen     = RegInit(0.U(12.W))
  // val isRxBusy  = RegInit(false.B)
@@ -209,24 +205,23 @@ trait TLCDRRx{ this: TLCDRBase =>

 }

-class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with TLCDRTx with TLCDRRx{
+class TLCDR()(implicit p: Parameters) extends TLCDRBase() with TLCDRTx with TLCDRRx{
+
+  val isWriteTransDir       = io.mem.fire & io.mem.addr(4,0) === "hc".U & io.mem.wstrb =/= 0.U
+

-  val isWriteTransDir       = io.tla.fire & io.tla.bits.address(4,0) === "hc".U & ( (io.tla.bits.opcode === 0.U) || (io.tla.bits.opcode === 1.U) )

-  val tlaInfo = Reg(new TLBundleA(edge.bundle))
-  val rdata = Reg(UInt(32.W))
-  val tlAReady  = RegInit(true.B)
-  val tlDValid = RegInit(false.B)

-  val isRead = tlaInfo.opcode === 4.U

  when( isWriteTransDir ){
-    dirSel := io.tla.bits.data
+    dirSel := io.mem.wdata
  }

+  io.mem.ready := 
+    ( io.mem.wstrb =/= 0.U & txFifo.io.enq.ready) | 
+    ( io.mem.wstrb === 0.U & Mux( io.mem.addr(4,0) === "h1c".U, rxFifo.io.deq.valid, true.B ) )
+

-  io.tla.ready := tlAReady & txFifo.io.enq.ready & ( Mux(io.tla.bits.address(4,0) === "h1c".U & ( io.tla.bits.opcode === 4.U ), rxFifo.io.deq.valid, true.B) )
-  io.tld.valid := tlDValid 

  io.interrupt(0) := intTxError
  io.interrupt(1) := intRxError
@@ -234,32 +229,15 @@ class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with
  io.interrupt(3) := intRxEnd


-  when( io.tla.fire ) {
-    tlaInfo := io.tla.bits
-  }
+  io.mem.rdata :=
+    Mux1H(Seq(
+      isTLReadStatus -> Cat( isRxValid, isRxError, isTxBusy, isTxFull, isTxError),
+      isTLReadRxLen  -> rxLen,
+      isTLReadRxFifo -> rxFifo.io.deq.bits
+    ))

-  when( io.tla.fire ){
-    tlAReady := false.B
-    tlDValid := true.B
-  } .elsewhen( io.tld.fire ) {
-    tlAReady := true.B
-    tlDValid := false.B
-  }

-  when(isRead) {
-    io.tld.bits := edge.AccessAck(tlaInfo, rdata)
-  } .otherwise {
-    io.tld.bits := edge.AccessAck(tlaInfo)
-  }
-  

-  when( isTLReadStatus){
-    rdata := Cat( isRxValid, isRxError, isTxBusy, isTxFull, isTxError )
-  } .elsewhen(isTLReadRxLen       ){
-    rdata := rxLen
-  } .elsewhen(isTLReadRxFifo      ){
-    rdata := rxFifo.io.deq.bits
-  }

 }