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发送单元 接收单元代码收尾

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This commit is contained in:
Ruige Lee
2025-04-09 17:29:57 +08:00
parent d7b04710ae
commit dabfc86983
4 changed files with 179 additions and 59 deletions
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98
src/main/scala/backBoard/shin/SlaveRecParser.scala
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@@ -24,21 +24,41 @@ class SlaveRecParserIO extends Module{
class SlaveRecParser extends Module{
val io: SlaveRecParserIO = IO(new SlaveRecParserIO)
val crc = Module(new crc32_8)
crc.io.isEnable :=
stateCurr === STATE_HEADER |
stateCurr === STATE_PAYLOAD_INDEX_STYLE |
stateCurr === STATE_PAYLOAD_ADDR |
stateCurr === STATE_PAYLOAD_OP_LENGTH |
stateCurr === STATE_PAYLOAD_WORKCNT |
stateCurr === STATE_PAYLOAD_DATA
crc.io.dataIn := io.rec.bits.tdata
crc.reset := reset.asBool | stateCurr === STATE_IDLE
val crcData = Reg(UInt(32.W))
val isCrcPass = crc.io.crc === Cat( crcData << 8, io.rec.bits.tdata )
when( stateCurr === STATE_CRC ){
crcData := Cat( crcData << 8, io.rec.bits.tdata )
}
val FRAME_STYLE_COMMON = 0.U
val FRAME_STYLE_PROBE = 1.U
val STATE_IDLE = 0.U //空闲
val STATE_HEADER = 1.U //长度/ /保留2bits //包类型
val STATE_PAYLOAD_INDEX_STYLE = 2.U //子报文设备索引 //子报文类型
val STATE_PAYLOAD_ADDR = 3.U //子报文地址
val STATE_IDLE = 0.U //空闲
val STATE_HEADER = 1.U //长度/ /保留2bits //包类型
val STATE_PAYLOAD_INDEX_STYLE = 2.U //子报文设备索引 //子报文类型
val STATE_PAYLOAD_ADDR = 3.U //子报文地址
val STATE_PAYLOAD_OP_LENGTH = 4.U //子报文命令类型 //子报文长度
val STATE_PAYLOAD_WORKCNT = 5.U //子报文工作计数
val STATE_PAYLOAD_DATA = 6.U //子报文数据
val STATE_CRC = 7.U //CRC校验
val STATE_ERROR = 8.U //
val STATE_WAIT = 9.U
val STATE_PAYLOAD_WORKCNT = 5.U //子报文工作计数
val STATE_PAYLOAD_DATA = 6.U //子报文数据
val STATE_CRC = 7.U //CRC校验
val STATE_ERROR = 8.U //
val STATE_WAIT = 9.U
val stateNext = Wire(UInt(4.W)); io.stateNext := stateNext
@@ -46,18 +66,51 @@ class SlaveRecParser extends Module{
val lengthCnt = Reg(UInt(11.W)) //动态计数器
val frameLenCnt = Reg(UInt(12.W)) //帧长度计数
val isCrcPass: Bool
val isShortRx: Bool //接收长度小于预期
val frameLenAim = Reg(UInt(12.W)); io.frameLenAim := frameLenAim //帧长度目标
val frameStyle = Reg(UInt(2.W)); io.frameStyle := frameStyle //包类型
val devIndex = Reg(UInt(14.W)); io.subMsgReq.devIndex := devIndex // 子报文中设备索引
val style = Reg(UInt(2.W)); io.subMsgReq.style := style // 子报文类型
val address = Reg(UInt(16.W)); io.subMsgReq.address := address //子报文地址
val operator = Reg(UInt(4.W)); io.subMsgReq.operator := operator //子报文命令类型
val length = Reg(UInt(12.W)); io.subMsgReq.length := length //子报文负载长度
val workCnt = Reg(UInt(16.W)); io.subMsgReq.workCnt := workCnt //子报文工作计数
val isShortRx = ~io.rec.valid //接收长度小于预期
val frameLenAim = Reg(UInt(12.W)); io.frameReq.bits.frameLenAim := frameLenAim //帧长度目标
val frameStyle = Reg(UInt(2.W)); io.frameReq.bits.frameStyle := frameStyle //包类型
io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_PAYLOAD_INDEX_STYLE)
val devIndex = Reg(UInt(14.W)); io.subMsgReq.bits.devIndex := devIndex // 子报文中设备索引
val style = Reg(UInt(2.W)); io.subMsgReq.bits.style := style // 子报文类型
val address = Reg(UInt(16.W)); io.subMsgReq.bits.address := address //子报文地址
val operator = Reg(UInt(4.W)); io.subMsgReq.bits.operator := operator //子报文命令类型
val length = Reg(UInt(12.W)); io.subMsgReq.bits.length := length //子报文负载长度
val workCnt = Reg(UInt(16.W)); io.subMsgReq.bits.workCnt := workCnt //子报文工作计数
io.subMsgReq.valid := (stateCurr === STATE_PAYLOAD_WORKCNT) & (stateNext === STATE_PAYLOAD_DATA)
when( stateCurr === STATE_IDLE ){
lengthCnt := 0.U
} .elsewhen( stateCurr =/= stateNext ){
lengthCnt := 0.U
} .otherwise{
lengthCnt := lengthCnt + 1.U
}
when( stateCurr === STATE_IDLE || stateCurr === STATE_HEADER ){
frameLenCnt := 0.U
} .elsewhen(
( stateCurr === STATE_PAYLOAD_INDEX_STYLE ) ||
( stateCurr === STATE_PAYLOAD_ADDR ) ||
( stateCurr === STATE_PAYLOAD_OP_LENGTH ) ||
( stateCurr === STATE_PAYLOAD_WORKCNT ) ||
( stateCurr === STATE_PAYLOAD_DATA )
){
frameLenCnt := frameLenCnt + 1.U
}
io.data.valid := stateCurr === STATE_PAYLOAD_DATA
io.data.bits := io.rec.bits
assert( ~(io.data.valid & ~io.data.ready), "Assert Failed! Receive Data was recected by fifo!" )
when( stateCurr === STATE_HEADER & lengthCnt === 0.U ){
@@ -123,11 +176,10 @@ class SlaveRecParser extends Module{
Mux( frameLenCnt === frameLenAim, STATE_CRC, STATE_PAYLOAD_INDEX_STYLE
), STATE_PAYLOAD_DATA )
),
( stateCurr === STATE_CRC ) -> Mux( isShortRx, STATE_ERROR,
Mux( lengthCnt === (4 - 1).U, Mux( isCrcPass, STATE_IDLE, STATE_ERROR), STATE_CRC )
),
( stateCurr === STATE_CRC ) ->
Mux( lengthCnt === (4 - 1).U, Mux( isCrcPass, STATE_IDLE, STATE_ERROR), Mux( isShortRx, STATE_ERROR, STATE_CRC ) ),
( stateCurr === STATE_ERROR ) -> Mux( io.resp, STATE_IDLE, STATE_ERROR ),
( stateCurr === STATE_WAIT ) -> Mux( io.resp, STATE_IDLE, STATE_ERROR )
( stateCurr === STATE_WAIT ) -> Mux( io.resp, STATE_IDLE, STATE_WAIT )
))