From d90ea07f5e04268d83eafa71fe9d899fb98718d7 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Tue, 20 May 2025 17:21:02 +0800 Subject: [PATCH] =?UTF-8?q?spi=E8=AF=BB=E5=8F=96=E4=BF=AE=E5=A4=8D?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/SpiInterface.scala | 2 +- tb/shinTest/ShinTopSpiTb.v | 5 +---- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala index 0b3b5ac..7945590 100644 --- a/src/main/scala/backBoard/shin/SpiInterface.scala +++ b/src/main/scala/backBoard/shin/SpiInterface.scala @@ -137,7 +137,7 @@ class SSpiInterface extends SpiInterfaceBase{ when((byteSel === 1.U || byteSel === 2.U) ){ exRego := 0.U //地址1，cmd } .elsewhen( isSpiRead ){ - exRego := io.datar + exRego := readData } }.otherwise{ exRego := exRego << 1 diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v index 6cdae78..1eed35b 100644 --- a/tb/shinTest/ShinTopSpiTb.v +++ b/tb/shinTest/ShinTopSpiTb.v @@ -357,10 +357,7 @@ always @(posedge sck) begin exChangeRegi <= 0; end end else begin - if( isQspi ) begin - exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso}; - end - + exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso}; end end else begin isBusy <= #5 1'b0;