diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala
index 0b3b5ac..7945590 100644
--- a/src/main/scala/backBoard/shin/SpiInterface.scala
+++ b/src/main/scala/backBoard/shin/SpiInterface.scala
@@ -137,7 +137,7 @@ class SSpiInterface extends SpiInterfaceBase{
       when((byteSel === 1.U || byteSel === 2.U) ){
         exRego := 0.U //地址1，cmd
       } .elsewhen( isSpiRead ){
-        exRego := io.datar
+        exRego := readData
       }
     }.otherwise{
       exRego := exRego << 1
diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v
index 6cdae78..1eed35b 100644
--- a/tb/shinTest/ShinTopSpiTb.v
+++ b/tb/shinTest/ShinTopSpiTb.v
@@ -357,10 +357,7 @@ always @(posedge sck) begin
           exChangeRegi <= 0;
         end
       end else begin
-        if( isQspi ) begin
-          exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso};
-        end
-
+        exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso};
       end
     end else begin
       isBusy       <= #5 1'b0;