diff --git a/src/main/scala/backBoard/ebus/TL2CDR.scala b/src/main/scala/backBoard/ebus/TL2CDR.scala
index 73811af..696a620 100644
--- a/src/main/scala/backBoard/ebus/TL2CDR.scala
+++ b/src/main/scala/backBoard/ebus/TL2CDR.scala
@@ -309,32 +309,32 @@ with TL2CDRImplUserCRC
 with TL2CDRImplLimitTimmer
 {
 
-  isTLWriteSoftReset(0)     := bus.a.fire & bus.a.bits.address(5,0) === "h00".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
-  isTLWriteTxLen(0)         := bus.a.fire & bus.a.bits.address(5,0) === "h04".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
-  isTLWriteTxFifo(0)        := bus.a.fire & bus.a.bits.address(5,0) === "h08".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
-  isTLReadTxCrc(0)          := bus.a.fire & bus.a.bits.address(5,0) === "h0c".U &    bus.a.bits.opcode === 4.U
+  isTLWriteSoftReset(0)     := bus.a.fire & bus.a.bits.address(7,0) === "h00".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
+  isTLWriteTxLen(0)         := bus.a.fire & bus.a.bits.address(7,0) === "h04".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
+  isTLWriteTxFifo(0)        := bus.a.fire & bus.a.bits.address(7,0) === "h08".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
+  isTLReadTxCrc(0)          := bus.a.fire & bus.a.bits.address(7,0) === "h0c".U &    bus.a.bits.opcode === 4.U
   
-  isTLWriteSoftReset(1)     := bus.a.fire & bus.a.bits.address(5,0) === "h10".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
-  isTLWriteTxLen(1)         := bus.a.fire & bus.a.bits.address(5,0) === "h14".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
-  isTLWriteTxFifo(1)        := bus.a.fire & bus.a.bits.address(5,0) === "h18".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
-  isTLReadTxCrc(1)          := bus.a.fire & bus.a.bits.address(5,0) === "h1c".U &    bus.a.bits.opcode === 4.U
+  isTLWriteSoftReset(1)     := bus.a.fire & bus.a.bits.address(7,0) === "h10".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
+  isTLWriteTxLen(1)         := bus.a.fire & bus.a.bits.address(7,0) === "h14".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
+  isTLWriteTxFifo(1)        := bus.a.fire & bus.a.bits.address(7,0) === "h18".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
+  isTLReadTxCrc(1)          := bus.a.fire & bus.a.bits.address(7,0) === "h1c".U &    bus.a.bits.opcode === 4.U
   
-  isTLWriteSoftReset(2)     := bus.a.fire & bus.a.bits.address(5,0) === "h20".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
-  isTLReadRxLen(0)          := bus.a.fire & bus.a.bits.address(5,0) === "h24".U & (  bus.a.bits.opcode === 4.U )
-  isTLReadRxFifo(0)         := bus.a.fire & bus.a.bits.address(5,0) === "h28".U & (  bus.a.bits.opcode === 4.U )
-  isTLReadRxCrc(0)          := bus.a.fire & bus.a.bits.address(5,0) === "h2c".U &    bus.a.bits.opcode === 4.U
-  isTLWriteLimitTimerAim(0) := bus.a.fire & bus.a.bits.address(5,0) === "h30".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
-  isTLWriteLimitTxPair(0)   := bus.a.fire & bus.a.bits.address(5,0) === "h34".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
+  isTLWriteSoftReset(2)     := bus.a.fire & bus.a.bits.address(7,0) === "h20".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
+  isTLReadRxLen(0)          := bus.a.fire & bus.a.bits.address(7,0) === "h24".U & (  bus.a.bits.opcode === 4.U )
+  isTLReadRxFifo(0)         := bus.a.fire & bus.a.bits.address(7,0) === "h28".U & (  bus.a.bits.opcode === 4.U )
+  isTLReadRxCrc(0)          := bus.a.fire & bus.a.bits.address(7,0) === "h2c".U &    bus.a.bits.opcode === 4.U
+  isTLWriteLimitTimerAim(0) := bus.a.fire & bus.a.bits.address(7,0) === "h30".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
+  isTLWriteLimitTxPair(0)   := bus.a.fire & bus.a.bits.address(7,0) === "h34".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
   
-  isTLWriteSoftReset(3)     := bus.a.fire & bus.a.bits.address(5,0) === "h40".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
-  isTLReadRxLen(1)          := bus.a.fire & bus.a.bits.address(5,0) === "h44".U & (  bus.a.bits.opcode === 4.U )
-  isTLReadRxFifo(1)         := bus.a.fire & bus.a.bits.address(5,0) === "h48".U & (  bus.a.bits.opcode === 4.U )
-  isTLReadRxCrc(1)          := bus.a.fire & bus.a.bits.address(5,0) === "h4c".U &    bus.a.bits.opcode === 4.U
-  isTLWriteLimitTimerAim(1) := bus.a.fire & bus.a.bits.address(5,0) === "h50".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
-  isTLWriteLimitTxPair(1)   := bus.a.fire & bus.a.bits.address(5,0) === "h54".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
+  isTLWriteSoftReset(3)     := bus.a.fire & bus.a.bits.address(7,0) === "h40".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
+  isTLReadRxLen(1)          := bus.a.fire & bus.a.bits.address(7,0) === "h44".U & (  bus.a.bits.opcode === 4.U )
+  isTLReadRxFifo(1)         := bus.a.fire & bus.a.bits.address(7,0) === "h48".U & (  bus.a.bits.opcode === 4.U )
+  isTLReadRxCrc(1)          := bus.a.fire & bus.a.bits.address(7,0) === "h4c".U &    bus.a.bits.opcode === 4.U
+  isTLWriteLimitTimerAim(1) := bus.a.fire & bus.a.bits.address(7,0) === "h50".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
+  isTLWriteLimitTxPair(1)   := bus.a.fire & bus.a.bits.address(7,0) === "h54".U & ( (bus.a.bits.opcode === 0.U) || (bus.a.bits.opcode === 1.U) )
   
-  isTLReadStatus         := bus.a.fire & bus.a.bits.address(5,0) === "h58".U & ( bus.a.bits.opcode === 4.U )
-  isReadIsLast           := bus.a.fire & bus.a.bits.address(5,0) === "h5c".U & ( bus.a.bits.opcode === 4.U )
+  isTLReadStatus         := bus.a.fire & bus.a.bits.address(7,0) === "h58".U & ( bus.a.bits.opcode === 4.U )
+  isReadIsLast           := bus.a.fire & bus.a.bits.address(7,0) === "h5c".U & ( bus.a.bits.opcode === 4.U )
 
   int(0) := intTxEnd(0)
   int(1) := intTxEnd(1)
@@ -371,8 +371,8 @@ with TL2CDRImplLimitTimmer
   bus.a.ready :=
     tlAReady &
     MuxCase( true.B, Array(
-      ( bus.a.bits.address(5,0) === "h08".U ) -> txFifo(0).io.enq.ready,
-      ( bus.a.bits.address(5,0) === "h18".U ) -> txFifo(1).io.enq.ready,
+      ( bus.a.bits.address(7,0) === "h08".U ) -> txFifo(0).io.enq.ready,
+      ( bus.a.bits.address(7,0) === "h18".U ) -> txFifo(1).io.enq.ready,
       ( bus.a.bits.address(7,0) === "h28".U ) -> rxFifo(0).io.deq.valid,
       ( bus.a.bits.address(7,0) === "h48".U ) -> rxFifo(1).io.deq.valid,
     ))