接收数据流解耦初步测试成功

2023-10-18 17:11:56 +08:00
parent 629d9486d1
commit d77c69aa5a
3 changed files with 1359 additions and 1 deletions
--- a/src/main/scala/mac/MacTilelink.scala
+++ b/src/main/scala/mac/MacTilelink.scala
@@ -99,7 +99,7 @@ abstract class MacTileLinkBase() extends Module{
  rxBuff.io.enq.data.bits := io.RxDataLatched2_rxclk
  rxBuff.io.enq.data.valid := WriteRxDataToFifoSyncPluse 

-  assert( (~rxBuff.io.enq.data.valid & ~rxBuff.io.enq.data.ready), "Assert Failed, rx overrun!" )
+  assert( ~(rxBuff.io.enq.data.valid & ~rxBuff.io.enq.data.ready), "Assert Failed, rx overrun!" )



@@ -258,6 +258,7 @@ class MacTileLink() extends MacTileLinkBase(){

  rxBuff.io.deq.data.ready := false.B
  rxBuff.io.deq.ctrl.ready := false.B
+
 }