接收数据流解耦初步测试成功

src/main/scala/mac/MacTilelink.scala

@@ -99,7 +99,7 @@ abstract class MacTileLinkBase() extends Module{
   rxBuff.io.enq.data.bits := io.RxDataLatched2_rxclk
   rxBuff.io.enq.data.valid := WriteRxDataToFifoSyncPluse 
 
-  assert( (~rxBuff.io.enq.data.valid & ~rxBuff.io.enq.data.ready), "Assert Failed, rx overrun!" )
+  assert( ~(rxBuff.io.enq.data.valid & ~rxBuff.io.enq.data.ready), "Assert Failed, rx overrun!" )
 
 
 
@@ -258,6 +258,7 @@ class MacTileLink() extends MacTileLinkBase(){
 
   rxBuff.io.deq.data.ready := false.B
   rxBuff.io.deq.ctrl.ready := false.B
+
 }
 
 

src/main/scala/mac/RxBuff.scala

@@ -46,6 +46,10 @@ class RxBuff extends Module{
 
   val pipoBuff = for( i <- 0 until 2 ) yield { Module(new Queue( UInt(32.W), 2048/4 )) }
   val pipoInfo = for( i <- 0 until 2 ) yield { Reg(new Packet_Info_Bundle) }
+  dontTouch(pipoBuff(0).io.enq)
+  dontTouch(pipoInfo(0))
+  dontTouch(pipoBuff(1).io.enq)
+  dontTouch(pipoInfo(1))
 
   val recCnt = RegInit(0.U(3.W))