From d760ecff08d647774f5df3ce7af8fa9abcbdeb89 Mon Sep 17 00:00:00 2001
From: bacon <bacon@rtems.cn>
Date: Wed, 16 Jul 2025 14:46:02 +0800
Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E8=B6=85=E6=97=B6=E5=81=9C?=
 =?UTF-8?q?=E6=AD=A2=E7=9A=84=E4=BB=A3=E7=A0=81?=
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---
 tb/shinTest/ShinTopSpiTb.v | 42 +++++++++++++++++++++++++++++++++++---
 tb/shinTest/gen_pkt.py     |  3 ++-
 2 files changed, 41 insertions(+), 4 deletions(-)

diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v
index 4b434c8..e1709eb 100644
--- a/tb/shinTest/ShinTopSpiTb.v
+++ b/tb/shinTest/ShinTopSpiTb.v
@@ -1,9 +1,9 @@
 `timescale 1 ns / 1 ps
 
 `define ENABLE_REG_RW_TEST
-//`define ENABLE_DET_TEST
-//`define ENABLE_SET_ADDR_TEST
-//`define ENABLE_INT_INIT_TEST
+`define ENABLE_DET_TEST
+`define ENABLE_SET_ADDR_TEST
+`define ENABLE_INT_INIT_TEST
 `define ENABLE_DET_ERR_TEST
 //`define ENABLE_SM1_SEND_TEST
 //`define ENABLE_SMx_SEND_TEST
@@ -67,6 +67,10 @@ module ShinTopSpiTb(
 
     wire [4:0] io_int_sig;
 
+    reg _reset_deadline_ind;
+    reg _deadline_ind;
+    reg[31:0] _deadline_ind_ctr;
+
 ShinTop s_ShinTop_Mst(
   .clock(clock),
   .reset(reset | isSoftReset[0]),
@@ -246,6 +250,10 @@ initial begin
   clk8x = 0;
 	reset = 1;
 
+  _reset_deadline_ind = 0;
+  _deadline_ind = 0;
+  _deadline_ind_ctr = 0;
+
   _reset_deactive = 1'b0;
 
   $timeformat(-9, 2, " ns", 8);
@@ -283,6 +291,21 @@ begin
 	$dumpvars(0, ShinTopSpiTb);//tb模块名称
 end
 
+always @(posedge clock or posedge _reset_deadline_ind) begin
+  if (_reset_deadline_ind == 1) begin
+    _deadline_ind_ctr <= 0;
+    #30 _reset_deadline_ind <= 0;
+  end
+  else begin
+    _deadline_ind_ctr <= _deadline_ind_ctr + 1;
+  end
+  if (_deadline_ind_ctr >= 10000) begin
+    _deadline_ind <= 1;
+  end
+  else begin
+    _deadline_ind <= 0;
+  end
+end
 
 always @(posedge reset) begin
   _reset_deactive <= 1'b0;
@@ -710,6 +733,12 @@ initial begin
     spi_trans( (16'h00), (`SPI_READ), (1), (`IF_IDX(2)) );
     spi_trans( (16'h00), (`SPI_READ), (1), (`IF_IDX(3)) );
     spi_trans( (16'h00), (`SPI_READ), (1), (`IF_IDX(4)) );
+    /*
+    $display("------------------------------ start! %t", $realtime);
+    _reset_deadline_ind = 1;
+    @(posedge _deadline_ind) #5 begin end
+    $display("------------------------------ End! %t", $realtime);
+    */
   end
 
 `ifdef ENABLE_INT_INIT_TEST
@@ -748,6 +777,13 @@ initial begin
     spi_trans( (16'h70), (`SPI_READ), (14), (`IF_IDX(2)) );
     spi_trans( (16'h70), (`SPI_READ), (14), (`IF_IDX(3)) );
     spi_trans( (16'h70), (`SPI_READ), (14), (`IF_IDX(4)) );
+    
+    /*
+    $display("------------------------------ start! %t", $realtime);
+    _reset_deadline_ind = 1;
+    @(posedge _deadline_ind) #5 begin end
+    $display("------------------------------ End! %t", $realtime);
+    */
   end
 
   begin:CHECK_INTERRUPT_CFG_REG
diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py
index a28bd2c..63b1ae5 100755
--- a/tb/shinTest/gen_pkt.py
+++ b/tb/shinTest/gen_pkt.py
@@ -223,7 +223,8 @@ def genTrgTransPktCode(gen_name, sm_idx):
         
 def genReadAckPktCode(gen_name, sm_idx):
     return '''\n//等待回包\n'''\
-        + '''@(posedge isResp) #5 begin end\n'''\
+        + '''_reset_deadline_ind = 1;\n'''\
+        + '''@(posedge isResp or posedge _deadline_ind) #5 begin end\n'''\
         + '''$fdisplay(spidata_file, ">>回包：");\n'''\
         + '''spi_trans( (`MST_RX%d_ADDR), (`SPI_READ), (`DEF_%s_len), (`IF_IDX(0)) );\n'''%(sm_idx, gen_name,)