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FSMC重构，使用100MHZ过采样

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This commit is contained in:
RuigeLee
2024-01-08 18:01:29 +08:00
parent b15cb7117c
commit d74a4754a7
4 changed files with 230 additions and 230 deletions
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269
src/main/scala/backBoard/BackBoardMst.scala
View File

@@ -8,26 +8,24 @@ import chisel3.util._
class FSMC_Port_Bundle extends Bundle{
// val addr = Input(UInt(10.W))
val ADIn = Input(UInt(16.W))
val ADOut = Output(UInt(16.W))
val ADOEn = Output(Bool())
val csn = Input(Bool())
val rdn = Input(Bool())
val wrn = Input(Bool())
val advn = Input(Bool())
val cs = Input(Bool())
val rd = Input(Bool())
val wr = Input(Bool())
val adv = Input(Bool())
}
class BackBoardMstIO extends Bundle{
// val FSMC = new FSMC_Port_Bundle
val FSMC = new FSMC_Port_Bundle
// val reset = Input(Bool())
val reset_calib = Input(Bool())
val oser_pclk = Input(Bool())
val oser_fclk = Input(Bool())
val ides_pclk = Input(Bool())
val ides_fclk = Input(Bool())
val oser_pclk = Input(Bool()) //10M
val oser_fclk = Input(Bool()) //50M
val ides_pclk = Input(Bool()) //100M
val ides_fclk = Input(Bool()) //400M
val lvds_down_dout = Output(Bool())
val lvds_up_din = Input(Bool())
@@ -36,8 +34,8 @@ val reset_calib = Input(Bool())
val crcErr = Output(Bool())
val linkErr = Output(Bool())
val testFail = Output(Bool())
val testDone = Output(Bool())
// val testFail = Output(Bool())
// val testDone = Output(Bool())
}
// class Master_Status_Bundle extends Bundle{
@@ -93,11 +91,11 @@ class BackBoardMstBase extends Module{ //10M
mirrorDown.io.clockw := io.oser_pclk.asBool
mirrorDown.io.clockr := io.oser_pclk.asBool
mirrorDown.io.clockr := io.oser_pclk.asBool
mirrorUp.io.clockw := io.oser_pclk.asBool
mirrorUp.io.clockr := io.oser_pclk.asBool
io.cdrErr := statusCDRErr
@@ -109,126 +107,135 @@ class BackBoardMstBase extends Module{ //10M
// trait BackBoardMstFSMC{ this: BackBoardMstBase =>
trait BackBoardMstFSMC{ this: BackBoardMstBase =>
val isRegRefleshFlip = withClockAndReset( io.ides_pclk.asClock, reset ){ RegInit(false.B) }
val wrRegAddr = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(10.W)) }
val wrRegData = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(16.W)) }
withClockAndReset( io.ides_pclk.asClock, reset ){//100M
mirrorDown.io.clockw := io.ides_pclk.asBool
mirrorUp.io.clockr := io.ides_pclk.asBool
val fsmcCSSync = ShiftRegisters( io.FSMC.cs, 3, false.B, true.B )
val fsmcRDSync = ShiftRegisters( io.FSMC.rd, 3, false.B, true.B )
val fsmcWRSync = ShiftRegisters( io.FSMC.wr, 3, false.B, true.B )
val fsmcADVSync = ShiftRegisters( io.FSMC.adv, 3, false.B, true.B )
io.FSMC.ADOEn := fsmcRDSync(1)
val latchAddr = RegEnable( io.FSMC.ADIn, ~fsmcADVSync(2) & fsmcADVSync(1) )
val isAccessSRAM = ~latchAddr.extract(10)
val isAccessReg = latchAddr.extract(10)
val activeAddr = latchAddr(9,0)
val regOut = Wire(UInt(16.W))
val fsmcCSWRSync = ShiftRegisters( io.FSMC.cs & io.FSMC.wr, 3, false.B, true.B )
val fsmcCSRDSync = ShiftRegisters( io.FSMC.cs & io.FSMC.rd, 3, false.B, true.B )
mirrorDown.io.enw := isAccessSRAM & ~fsmcCSWRSync(2) & fsmcCSWRSync(1)
mirrorDown.io.addrw := activeAddr
mirrorDown.io.dataw := io.FSMC.ADIn
mirrorUp.io.enr := isAccessSRAM & ~fsmcCSRDSync(2) & fsmcCSRDSync(1)
mirrorUp.io.addrr := activeAddr
io.FSMC.ADOut := Mux( isAccessReg, regOut, mirrorUp.io.datar)
regOut := Mux1H(Seq(
( activeAddr === 0.U) ->
Cat(
statusCDRErr ,
statusCRCErr ,
statusLinkErr,
statusSynch ,
statusInit
),
( activeAddr === 1.U) ->
Cat(
ctrlTransmit,
0.U(1.W),
0.U(1.W),
0.U(1.W),
ctrlSynch,
ctrlInit
),
( activeAddr === 2.U) -> slvNum,
( activeAddr === 3.U) -> slvOffLine,
))
// // val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B )
// // val fsmcADInSync = ShiftRegister( io.FSMC.ADIn, 2, 0.U, true.B )
// val fsmcCSnSync = ShiftRegister( io.FSMC.csn, 2, true.B, true.B )
// val fsmcRDnSync = ShiftRegister( io.FSMC.rdn, 2, true.B, true.B )
// val fsmcWRnSync = ShiftRegister( io.FSMC.wrn, 2, true.B, true.B )
// val fsmcADVnSync = ShiftRegister( io.FSMC.advn, 2, true.B, true.B )
when( isAccessReg & ~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){
isRegRefleshFlip := ~isRegRefleshFlip
wrRegAddr := activeAddr
wrRegData := io.FSMC.ADIn
// io.FSMC.ADOEn := fsmcRDnSync
// val latchAddr = RegEnable( io.FSMC.ADIn, ~fsmcADVnSync )
// val isAccessSRAM = ~latchAddr.extract(9)
// val isAccessReg = latchAddr.extract(9)
// val activeAddr = latchAddr(8,0)
// val regOut = Wire(UInt(16.W))
// mirrorDown.io.enw := isAccessSRAM & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.wrn, 2, false.B, true.B )
// mirrorDown.io.addrw := activeAddr
// mirrorDown.io.dataw := io.FSMC.ADIn
// mirrorUp.io.enr := isAccessSRAM & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.rdn, 2, false.B, true.B )
// mirrorUp.io.addrr := activeAddr
// io.FSMC.ADOut := Mux( isAccessReg, regOut, mirrorUp.io.datar)
// regOut := Mux1H(Seq(
// ( activeAddr === 0.U) ->
// Cat(
// statusCDRErr ,
// statusCRCErr ,
// statusLinkErr,
// statusSynch ,
// statusInit
// ),
// ( activeAddr === 1.U) ->
// Cat(
// ctrlTransmit,
// 0.U(1.W),
// 0.U(1.W),
// 0.U(1.W),
// ctrlSynch,
// ctrlInit
// ),
// ( activeAddr === 2.U) -> slvNum,
// ( activeAddr === 3.U) -> slvOffLine,
// ))
// // when( isAccessReg & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.wrn, 2, false.B, true.B ) & ( activeAddr === 0.U) ){
// // status := io.FSMC.ADIn
// // }
// when( isAccessReg & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.wrn, 2, false.B, true.B ) & ( activeAddr === 1.U) ){
// ctrlTransmit := io.FSMC.ADIn.extract(5)
// when( io.FSMC.ADIn.extract(4) ){
// statusCDRErr := false.B
// }
// when( io.FSMC.ADIn.extract(3) ){
// statusCRCErr := false.B
// }
// when( io.FSMC.ADIn.extract(2) ){
// statusLinkErr := false.B
// }
// ctrlSynch := io.FSMC.ADIn.extract(1)
// ctrlInit := io.FSMC.ADIn.extract(0)
// }
// // when( (isAccessReg & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.wrn, 2, false.B, true.B ) ) & ( activeAddr === 2.U) ){
// // slvNum := io.FSMC.ADIn
// // }
// when( (isAccessReg & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.wrn, 2, false.B, true.B ) ) & ( activeAddr === 3.U) ){
// slvOffLine := io.FSMC.ADIn
// }
// }
trait BackBoardMstSim{ this: BackBoardMstLVDSBase =>
val ( powerUpCnt, isPowerUpTimeout ) = Counter(Range( 0,5200), ~ctrlInit & ~statusInit, false.B)
when( powerUpCnt === 500.U ){
ctrlInit := true.B
}
ctrlTransmit := statusInit
mirrorDown.io.enw := true.B
mirrorDown.io.addrw := powerUpCnt
mirrorDown.io.dataw := "h5555".U
}
//10M
val isChkRegReflesh = RegInit(false.B)
mirrorUp.io.enr := false.B
mirrorUp.io.addrr := 0.U
when( isChkRegReflesh =/= isRegRefleshFlip ){
when( wrRegAddr === 1.U ){
ctrlTransmit := wrRegData.extract(5)
when( wrRegData.extract(4) ){
statusCDRErr := false.B
}
when( wrRegData.extract(3) ){
statusCRCErr := false.B
}
when( wrRegData.extract(2) ){
statusLinkErr := false.B
}
ctrlSynch := wrRegData.extract(1)
ctrlInit := wrRegData.extract(0)
}
}
val testDone = RegInit(false.B)
val testFail = RegInit(false.B)
io.testDone := ~testDone
io.testFail := ~testFail
}
// trait BackBoardMstSim{ this: BackBoardMstLVDSBase =>
// val ( powerUpCnt, isPowerUpTimeout ) = Counter(Range( 0,5200), ~ctrlInit & ~statusInit, false.B)
// when( powerUpCnt === 500.U ){
// ctrlInit := true.B
// }
// ctrlTransmit := statusInit
// mirrorDown.io.enw := true.B
// mirrorDown.io.addrw := powerUpCnt
// mirrorDown.io.dataw := "h5555".U
// mirrorUp.io.enr := false.B
// mirrorUp.io.addrr := 0.U
// val testDone = RegInit(false.B)
// val testFail = RegInit(false.B)
// io.testDone := ~testDone
// io.testFail := ~testFail
// }
abstract class BackBoardMstLVDSBase extends BackBoardMstBase
// with BackBoardMstFSMC
with BackBoardMstSim
with BackBoardMstFSMC
// with BackBoardMstSim
{
@@ -269,7 +276,7 @@ trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>
frame_info_update_en := true.B
slave_type_num := Cat( "b00".U(2.W), slvNum )
slave_data_length := ((8/8)*16-1).U
slave_data_length := ((8/8)*32-1).U
tx_start := false.B
} .elsewhen( stateCur === 1.U ){ // tx start
@@ -301,7 +308,7 @@ trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>
frame_info_update_en := true.B
slave_type_num := Cat( "b00".U(2.W), slvNum )
slave_data_length := ((8/8)*16-1).U
slave_data_length := ((8/8)*32-1).U
tx_start := false.B
} .elsewhen( stateCur === 5.U ){ // tx start
@@ -317,11 +324,11 @@ trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>
when( lvdsMst.io.slave_link_num_valid ){
when( slvNum === lvdsMst.io.slave_link_num - 1.U ){
stateCur := 7.U
testDone := true.B
testFail := false.B
// testDone := true.B
// testFail := false.B
} .otherwise{
testDone := false.B
testFail := true.B
// testDone := false.B
// testFail := true.B
printf("Initialization failed, waitting for timeout!\n")
}
}
@@ -349,7 +356,7 @@ trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>
frame_info_update_en := true.B
slave_type_num := Cat( "b01".U(2.W), slvNum )
slave_data_length := ((8/8)*16-1).U
slave_data_length := ((8/8)*32-1).U
tx_start := false.B
} .elsewhen( stateCur === 10.U ){ // tx start
@@ -394,9 +401,9 @@ trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>
trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
val trigger = ctrlTransmit & ~RegNext(ctrlTransmit, false.B)
val ( _, trigger ) = Counter(Range( 0,1000), ctrlTransmit )
// val ( _, trigger ) = Counter(Range( 0,1000), ctrlTransmit )
when(ctrlTransmit){
when( trigger ){ //reset
@@ -414,7 +421,7 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
frame_info_update_en := true.B
slave_type_num := Cat( "b10".U(2.W), slvNum )
slave_data_length := ((8/8)*16-1).U
slave_data_length := ((8/8)*32-1).U
tx_start := false.B
} .elsewhen( stateCur === 1.U ){ // tx start
@@ -432,15 +439,15 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
}
} .elsewhen( stateCur === 3.U ){
ctrlTransmit := false.B
} .otherwise{
}
}
val addrr = RegInit(0.U(10.W))
val addrw = RegInit(0.U(10.W))
val addrr = RegInit(0.U(11.W))
val addrw = RegInit(0.U(11.W))
when( trigger ){
addrw := 0.U

16
src/main/scala/backBoard/BackBoardSlv.scala
View File

@@ -38,9 +38,9 @@ abstract class BackBoardSlvBase extends Module{
lvdsSlv.io.lvds_up_din := io.lvds_up_din
io.lvds_up_dout := lvdsSlv.io.lvds_up_dout
val downRegTemp = RegInit(VecInit(Seq.fill(16){0.U(8.W)}))
val downReg = RegInit(VecInit(Seq.fill(16){0.U(8.W)}))
val upReg = RegInit(VecInit((0 until 16).map{i => i.U(8.W)}))
val downRegTemp = RegInit(VecInit(Seq.fill(32){0.U(8.W)}))
val downReg = RegInit(VecInit(Seq.fill(32){0.U(8.W)}))
val upReg = RegInit(VecInit((0 until 32).map{i => i.U(8.W)}))
}
@@ -67,7 +67,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
when( downTimeout ){
downTimeoutEn := false.B
} .elsewhen( downCnt === 16.U ){
} .elsewhen( downCnt === 32.U ){
downTimeoutEn := false.B
} .elsewhen(downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid){
downTimeoutEn := true.B
@@ -75,7 +75,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
when( downTimeout ){
downCnt := 0.U
}.elsewhen( downCnt === 16.U ){
}.elsewhen( downCnt === 32.U ){
downCnt := 0.U
}.elsewhen( lvdsSlv.io.downstream_rx_data_valid ){
downCnt := downCnt + 1.U
@@ -86,7 +86,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
trait BackBoardSlvUp{ this: BackBoardSlvBase =>
val upCnt = RegInit(15.U(6.W))
val upCnt = RegInit(31.U(6.W))
val upTimeoutEn = RegInit( false.B )
val upTimeoutRst = (upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready)
val ( _, upTimeout ) = Counter( Range( 0,1000 ), upTimeoutEn, upTimeoutRst )
@@ -98,7 +98,7 @@ trait BackBoardSlvUp{ this: BackBoardSlvBase =>
when( upTimeout ){
upTimeoutEn := false.B
} .elsewhen( upCnt === 15.U ){
} .elsewhen( upCnt === 31.U ){
upTimeoutEn := false.B
} .elsewhen(upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready){
upTimeoutEn := true.B
@@ -107,7 +107,7 @@ trait BackBoardSlvUp{ this: BackBoardSlvBase =>
when( upTimeout ){
upCnt := 0.U
}.elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
when(upCnt === 15.U){
when(upCnt === 31.U){
upCnt := 0.U
} .elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
upCnt := upCnt + 1.U

144
src/main/scala/backBoard/MirrorSRAM.scala
View File

@@ -58,75 +58,75 @@ import chisel3.util._
// val reset = Input(Bool())
class MirrorSRAM(dw: Int, cl: Int) extends BlackBox with HasBlackBoxInline {
require(dw == 8)
require(cl == 2048)
class MirrorSRAMIO extends Bundle{
val addrr = Input(UInt(11.W))
val addrw = Input(UInt(11.W))
// class MirrorSRAM(dw: Int, cl: Int) extends BlackBox with HasBlackBoxInline {
// require(dw == 8)
// require(cl == 2048)
// class MirrorSRAMIO extends Bundle{
// val addrr = Input(UInt(11.W))
// val addrw = Input(UInt(11.W))
val dataw = Input( UInt(8.W) )
val datar = Output( UInt(8.W) )
val enw = Input(Bool())
val enr = Input(Bool())
// val dataw = Input( UInt(8.W) )
// val datar = Output( UInt(8.W) )
// val enw = Input(Bool())
// val enr = Input(Bool())
val clockr = Input(Bool())
val clockw = Input(Bool())
// val clockr = Input(Bool())
// val clockw = Input(Bool())
}
val io: MirrorSRAMIO = IO(new MirrorSRAMIO)
// }
// val io: MirrorSRAMIO = IO(new MirrorSRAMIO)
setInline("MirrorSRAM.v",
"""
| module MirrorSRAM(
| input [7:0] dataw,
| input [10:0] addrw,
| input enw,
|
| output [7:0] datar,
| input [10:0] addrr,
| input enr,
|
| input clockr,
| input clockw
| );
|
| reg [7:0] ram[0:2047];
| reg [7:0] data_r_reg;
|
| always @(posedge clockw) begin
| if(enw) begin
| ram[addrw] <= #1 dataw;
| end
| end
|
| always @(posedge clockr) begin
| if(enr) begin
| data_r_reg <= #1 ram[addrr];
| end
| end
|
| assign datar = data_r_reg;
|
| initial begin
| for ( integer i = 0; i < 2048; i = i + 1 ) begin
| ram[i] = $random;
| end
|
| data_r_reg = $random;
| end
|
|endmodule
""".stripMargin)
}
// setInline("MirrorSRAM.v",
// """
// | module MirrorSRAM(
// | input [7:0] dataw,
// | input [10:0] addrw,
// | input enw,
// |
// | output [7:0] datar,
// | input [10:0] addrr,
// | input enr,
// |
// | input clockr,
// | input clockw
// | );
// |
// | reg [7:0] ram[0:2047];
// | reg [7:0] data_r_reg;
// |
// | always @(posedge clockw) begin
// | if(enw) begin
// | ram[addrw] <= #1 dataw;
// | end
// | end
// |
// | always @(posedge clockr) begin
// | if(enr) begin
// | data_r_reg <= #1 ram[addrr];
// | end
// | end
// |
// | assign datar = data_r_reg;
// |
// | initial begin
// | for ( integer i = 0; i < 2048; i = i + 1 ) begin
// | ram[i] = $random;
// | end
// |
// | data_r_reg = $random;
// | end
// |
// |endmodule
// """.stripMargin)
// }
class MirrorSRAMDown() extends BlackBox with HasBlackBoxInline {
class MirrorSRAMDownIO extends Bundle{
val addrr = Input(UInt(10.W))
val addrw = Input(UInt(9.W))
val addrr = Input(UInt(11.W))
val addrw = Input(UInt(10.W))
val dataw = Input( UInt(16.W) )
val datar = Output( UInt(8.W) )
@@ -143,18 +143,18 @@ class MirrorSRAMDown() extends BlackBox with HasBlackBoxInline {
"""
| module MirrorSRAMDown(
| input [15:0] dataw,
| input [8:0] addrw,
| input [9:0] addrw,
| input enw,
|
| output [7:0] datar,
| input [9:0] addrr,
| input [10:0] addrr,
| input enr,
|
| input clockr,
| input clockw
| );
|
| reg [15:0] ram[0:511];
| reg [15:0] ram[0:1023];
| reg [7:0] data_r_reg;
|
| always @(posedge clockw) begin
@@ -165,14 +165,14 @@ class MirrorSRAMDown() extends BlackBox with HasBlackBoxInline {
|
| always @(posedge clockr) begin
| if(enr) begin
| data_r_reg <= #1 addrr[0] ? ram[addrr[9:1]][15:8] : ram[addrr[9:1]][7:0];
| data_r_reg <= #1 addrr[0] ? ram[addrr[10:1]][15:8] : ram[addrr[10:1]][7:0];
| end
| end
|
| assign datar = data_r_reg;
|
| initial begin
| for ( integer i = 0; i < 512; i = i + 1 ) begin
| for ( integer i = 0; i < 1024; i = i + 1 ) begin
| ram[i] = $random;
| end
|
@@ -187,8 +187,8 @@ class MirrorSRAMDown() extends BlackBox with HasBlackBoxInline {
class MirrorSRAMUp extends BlackBox with HasBlackBoxInline {
class MirrorSRAMUpIO extends Bundle{
val addrr = Input(UInt(9.W))
val addrw = Input(UInt(10.W))
val addrr = Input(UInt(10.W))
val addrw = Input(UInt(11.W))
val dataw = Input( UInt(8.W) )
val datar = Output( UInt(16.W) )
@@ -205,26 +205,26 @@ class MirrorSRAMUp extends BlackBox with HasBlackBoxInline {
"""
| module MirrorSRAMUp(
| input [7:0] dataw,
| input [9:0] addrw,
| input [10:0] addrw,
| input enw,
|
| output [15:0] datar,
| input [8:0] addrr,
| input [9:0] addrr,
| input enr,
|
| input clockr,
| input clockw
| );
|
| reg [15:0] ram[0:511];
| reg [15:0] ram[0:1023];
| reg [15:0] data_r_reg;
|
| always @(posedge clockw) begin
| if(enw) begin
| if( addrw[0] ) begin
| ram[addrw[9:1]][15:8] <= #1 dataw;
| ram[addrw[10:1]][15:8] <= #1 dataw;
| end else begin
| ram[addrw[9:1]][7:0] <= #1 dataw;
| ram[addrw[10:1]][7:0] <= #1 dataw;
| end
| end
| end
@@ -238,7 +238,7 @@ class MirrorSRAMUp extends BlackBox with HasBlackBoxInline {
| assign datar = data_r_reg;
|
| initial begin
| for ( integer i = 0; i < 512; i = i + 1 ) begin
| for ( integer i = 0; i < 1024; i = i + 1 ) begin
| ram[i] = $random;
| end
|

41
src/main/verilog/backBoardMstTop.v
View File

@@ -12,21 +12,17 @@ module master_top(
output lvds_down_dout_p,
output lvds_down_dout_n,
input [15:0] io_FSMC_dataIn,
output [15:0] io_FSMC_dataOut,
output io_FSMC_dataOEn,
input io_FSMC_ce,
input io_FSMC_oe,
input io_FSMC_we,
input io_FSMC_adv,
output cdrErr ,
output crcErr ,
output linkErr,
output testDone,
output testFail
// input [9:0] io_FSMC_addr,
// input [15:0] io_FSMC_dataIn,
// output [15:0] io_FSMC_dataOut,
// output io_FSMC_dataOEn,
// input io_FSMC_cen,
// input io_FSMC_oen,
// input io_FSMC_wen
output linkErr
);
wire clk_400m;
@@ -129,13 +125,13 @@ CLKDIV Inst5_CLKDIVC(
BackBoardMst i_BackBoardMst(
// .io_FSMC_addr(io_FSMC_addr),
// .io_FSMC_dataIn(io_FSMC_dataIn),
// .io_FSMC_dataOut(io_FSMC_dataOut),
// .io_FSMC_dataOEn(io_FSMC_dataOEn),
// .io_FSMC_cen(io_FSMC_cen),
// .io_FSMC_oen(io_FSMC_oen),
// .io_FSMC_wen(io_FSMC_wen),
.io_FSMC_dataIn(io_FSMC_dataIn),
.io_FSMC_dataOut(io_FSMC_dataOut),
.io_FSMC_dataOEn(io_FSMC_dataOEn),
.io_FSMC_ce(io_FSMC_ce),
.io_FSMC_oe(io_FSMC_oe),
.io_FSMC_we(io_FSMC_we),
.io_FSMC_adv(io_FSMC_adv),
.reset(~rst_n),
.clock(clk_10m_a),
@@ -150,10 +146,7 @@ BackBoardMst i_BackBoardMst(
.io_cdrErr (cdrErr),
.io_crcErr (crcErr),
.io_linkErr(linkErr),
.io_testDone(testDone),
.io_testFail(testFail)
.io_linkErr(linkErr)
);