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FSMC重构，使用100MHZ过采样

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RuigeLee
2024-01-08 18:01:29 +08:00
parent b15cb7117c
commit d74a4754a7
4 changed files with 230 additions and 230 deletions
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144
src/main/scala/backBoard/MirrorSRAM.scala
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@@ -58,75 +58,75 @@ import chisel3.util._
// val reset = Input(Bool())
class MirrorSRAM(dw: Int, cl: Int) extends BlackBox with HasBlackBoxInline {
require(dw == 8)
require(cl == 2048)
class MirrorSRAMIO extends Bundle{
val addrr = Input(UInt(11.W))
val addrw = Input(UInt(11.W))
// class MirrorSRAM(dw: Int, cl: Int) extends BlackBox with HasBlackBoxInline {
// require(dw == 8)
// require(cl == 2048)
// class MirrorSRAMIO extends Bundle{
// val addrr = Input(UInt(11.W))
// val addrw = Input(UInt(11.W))
val dataw = Input( UInt(8.W) )
val datar = Output( UInt(8.W) )
val enw = Input(Bool())
val enr = Input(Bool())
// val dataw = Input( UInt(8.W) )
// val datar = Output( UInt(8.W) )
// val enw = Input(Bool())
// val enr = Input(Bool())
val clockr = Input(Bool())
val clockw = Input(Bool())
// val clockr = Input(Bool())
// val clockw = Input(Bool())
}
val io: MirrorSRAMIO = IO(new MirrorSRAMIO)
// }
// val io: MirrorSRAMIO = IO(new MirrorSRAMIO)
setInline("MirrorSRAM.v",
"""
| module MirrorSRAM(
| input [7:0] dataw,
| input [10:0] addrw,
| input enw,
|
| output [7:0] datar,
| input [10:0] addrr,
| input enr,
|
| input clockr,
| input clockw
| );
|
| reg [7:0] ram[0:2047];
| reg [7:0] data_r_reg;
|
| always @(posedge clockw) begin
| if(enw) begin
| ram[addrw] <= #1 dataw;
| end
| end
|
| always @(posedge clockr) begin
| if(enr) begin
| data_r_reg <= #1 ram[addrr];
| end
| end
|
| assign datar = data_r_reg;
|
| initial begin
| for ( integer i = 0; i < 2048; i = i + 1 ) begin
| ram[i] = $random;
| end
|
| data_r_reg = $random;
| end
|
|endmodule
""".stripMargin)
}
// setInline("MirrorSRAM.v",
// """
// | module MirrorSRAM(
// | input [7:0] dataw,
// | input [10:0] addrw,
// | input enw,
// |
// | output [7:0] datar,
// | input [10:0] addrr,
// | input enr,
// |
// | input clockr,
// | input clockw
// | );
// |
// | reg [7:0] ram[0:2047];
// | reg [7:0] data_r_reg;
// |
// | always @(posedge clockw) begin
// | if(enw) begin
// | ram[addrw] <= #1 dataw;
// | end
// | end
// |
// | always @(posedge clockr) begin
// | if(enr) begin
// | data_r_reg <= #1 ram[addrr];
// | end
// | end
// |
// | assign datar = data_r_reg;
// |
// | initial begin
// | for ( integer i = 0; i < 2048; i = i + 1 ) begin
// | ram[i] = $random;
// | end
// |
// | data_r_reg = $random;
// | end
// |
// |endmodule
// """.stripMargin)
// }
class MirrorSRAMDown() extends BlackBox with HasBlackBoxInline {
class MirrorSRAMDownIO extends Bundle{
val addrr = Input(UInt(10.W))
val addrw = Input(UInt(9.W))
val addrr = Input(UInt(11.W))
val addrw = Input(UInt(10.W))
val dataw = Input( UInt(16.W) )
val datar = Output( UInt(8.W) )
@@ -143,18 +143,18 @@ class MirrorSRAMDown() extends BlackBox with HasBlackBoxInline {
"""
| module MirrorSRAMDown(
| input [15:0] dataw,
| input [8:0] addrw,
| input [9:0] addrw,
| input enw,
|
| output [7:0] datar,
| input [9:0] addrr,
| input [10:0] addrr,
| input enr,
|
| input clockr,
| input clockw
| );
|
| reg [15:0] ram[0:511];
| reg [15:0] ram[0:1023];
| reg [7:0] data_r_reg;
|
| always @(posedge clockw) begin
@@ -165,14 +165,14 @@ class MirrorSRAMDown() extends BlackBox with HasBlackBoxInline {
|
| always @(posedge clockr) begin
| if(enr) begin
| data_r_reg <= #1 addrr[0] ? ram[addrr[9:1]][15:8] : ram[addrr[9:1]][7:0];
| data_r_reg <= #1 addrr[0] ? ram[addrr[10:1]][15:8] : ram[addrr[10:1]][7:0];
| end
| end
|
| assign datar = data_r_reg;
|
| initial begin
| for ( integer i = 0; i < 512; i = i + 1 ) begin
| for ( integer i = 0; i < 1024; i = i + 1 ) begin
| ram[i] = $random;
| end
|
@@ -187,8 +187,8 @@ class MirrorSRAMDown() extends BlackBox with HasBlackBoxInline {
class MirrorSRAMUp extends BlackBox with HasBlackBoxInline {
class MirrorSRAMUpIO extends Bundle{
val addrr = Input(UInt(9.W))
val addrw = Input(UInt(10.W))
val addrr = Input(UInt(10.W))
val addrw = Input(UInt(11.W))
val dataw = Input( UInt(8.W) )
val datar = Output( UInt(16.W) )
@@ -205,26 +205,26 @@ class MirrorSRAMUp extends BlackBox with HasBlackBoxInline {
"""
| module MirrorSRAMUp(
| input [7:0] dataw,
| input [9:0] addrw,
| input [10:0] addrw,
| input enw,
|
| output [15:0] datar,
| input [8:0] addrr,
| input [9:0] addrr,
| input enr,
|
| input clockr,
| input clockw
| );
|
| reg [15:0] ram[0:511];
| reg [15:0] ram[0:1023];
| reg [15:0] data_r_reg;
|
| always @(posedge clockw) begin
| if(enw) begin
| if( addrw[0] ) begin
| ram[addrw[9:1]][15:8] <= #1 dataw;
| ram[addrw[10:1]][15:8] <= #1 dataw;
| end else begin
| ram[addrw[9:1]][7:0] <= #1 dataw;
| ram[addrw[10:1]][7:0] <= #1 dataw;
| end
| end
| end
@@ -238,7 +238,7 @@ class MirrorSRAMUp extends BlackBox with HasBlackBoxInline {
| assign datar = data_r_reg;
|
| initial begin
| for ( integer i = 0; i < 512; i = i + 1 ) begin
| for ( integer i = 0; i < 1024; i = i + 1 ) begin
| ram[i] = $random;
| end
|