ruige/eb001
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

FSMC重构，使用100MHZ过采样

Browse Source
This commit is contained in:
RuigeLee
2024-01-08 18:01:29 +08:00
parent b15cb7117c
commit d74a4754a7
4 changed files with 230 additions and 230 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
src/main/scala/backBoard/BackBoardSlv.scala
View File

@@ -38,9 +38,9 @@ abstract class BackBoardSlvBase extends Module{
lvdsSlv.io.lvds_up_din := io.lvds_up_din
io.lvds_up_dout := lvdsSlv.io.lvds_up_dout
val downRegTemp = RegInit(VecInit(Seq.fill(16){0.U(8.W)}))
val downReg = RegInit(VecInit(Seq.fill(16){0.U(8.W)}))
val upReg = RegInit(VecInit((0 until 16).map{i => i.U(8.W)}))
val downRegTemp = RegInit(VecInit(Seq.fill(32){0.U(8.W)}))
val downReg = RegInit(VecInit(Seq.fill(32){0.U(8.W)}))
val upReg = RegInit(VecInit((0 until 32).map{i => i.U(8.W)}))
}
@@ -67,7 +67,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
when( downTimeout ){
downTimeoutEn := false.B
} .elsewhen( downCnt === 16.U ){
} .elsewhen( downCnt === 32.U ){
downTimeoutEn := false.B
} .elsewhen(downCnt === 0.U & lvdsSlv.io.downstream_rx_data_valid){
downTimeoutEn := true.B
@@ -75,7 +75,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
when( downTimeout ){
downCnt := 0.U
}.elsewhen( downCnt === 16.U ){
}.elsewhen( downCnt === 32.U ){
downCnt := 0.U
}.elsewhen( lvdsSlv.io.downstream_rx_data_valid ){
downCnt := downCnt + 1.U
@@ -86,7 +86,7 @@ trait BackBoardSlvDown{ this: BackBoardSlvBase =>
trait BackBoardSlvUp{ this: BackBoardSlvBase =>
val upCnt = RegInit(15.U(6.W))
val upCnt = RegInit(31.U(6.W))
val upTimeoutEn = RegInit( false.B )
val upTimeoutRst = (upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready)
val ( _, upTimeout ) = Counter( Range( 0,1000 ), upTimeoutEn, upTimeoutRst )
@@ -98,7 +98,7 @@ trait BackBoardSlvUp{ this: BackBoardSlvBase =>
when( upTimeout ){
upTimeoutEn := false.B
} .elsewhen( upCnt === 15.U ){
} .elsewhen( upCnt === 31.U ){
upTimeoutEn := false.B
} .elsewhen(upCnt === 0.U & lvdsSlv.io.upstream_tx_data_ready){
upTimeoutEn := true.B
@@ -107,7 +107,7 @@ trait BackBoardSlvUp{ this: BackBoardSlvBase =>
when( upTimeout ){
upCnt := 0.U
}.elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
when(upCnt === 15.U){
when(upCnt === 31.U){
upCnt := 0.U
} .elsewhen( lvdsSlv.io.upstream_tx_data_ready ){
upCnt := upCnt + 1.U