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FSMC重构，使用100MHZ过采样

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This commit is contained in:
RuigeLee
2024-01-08 18:01:29 +08:00
parent b15cb7117c
commit d74a4754a7
4 changed files with 230 additions and 230 deletions
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259
src/main/scala/backBoard/BackBoardMst.scala
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@@ -8,26 +8,24 @@ import chisel3.util._
class FSMC_Port_Bundle extends Bundle{
// val addr = Input(UInt(10.W))
val ADIn = Input(UInt(16.W))
val ADOut = Output(UInt(16.W))
val ADOEn = Output(Bool())
val csn = Input(Bool())
val rdn = Input(Bool())
val wrn = Input(Bool())
val advn = Input(Bool())
val cs = Input(Bool())
val rd = Input(Bool())
val wr = Input(Bool())
val adv = Input(Bool())
}
class BackBoardMstIO extends Bundle{
// val FSMC = new FSMC_Port_Bundle
val FSMC = new FSMC_Port_Bundle
// val reset = Input(Bool())
val reset_calib = Input(Bool())
val oser_pclk = Input(Bool())
val oser_fclk = Input(Bool())
val ides_pclk = Input(Bool())
val ides_fclk = Input(Bool())
val oser_pclk = Input(Bool()) //10M
val oser_fclk = Input(Bool()) //50M
val ides_pclk = Input(Bool()) //100M
val ides_fclk = Input(Bool()) //400M
val lvds_down_dout = Output(Bool())
val lvds_up_din = Input(Bool())
@@ -36,8 +34,8 @@ val reset_calib = Input(Bool())
val crcErr = Output(Bool())
val linkErr = Output(Bool())
val testFail = Output(Bool())
val testDone = Output(Bool())
// val testFail = Output(Bool())
// val testDone = Output(Bool())
}
// class Master_Status_Bundle extends Bundle{
@@ -93,11 +91,11 @@ class BackBoardMstBase extends Module{ //10M
mirrorDown.io.clockw := io.oser_pclk.asBool
mirrorDown.io.clockr := io.oser_pclk.asBool
mirrorDown.io.clockr := io.oser_pclk.asBool
mirrorUp.io.clockw := io.oser_pclk.asBool
mirrorUp.io.clockr := io.oser_pclk.asBool
io.cdrErr := statusCDRErr
@@ -109,126 +107,135 @@ class BackBoardMstBase extends Module{ //10M
// trait BackBoardMstFSMC{ this: BackBoardMstBase =>
trait BackBoardMstFSMC{ this: BackBoardMstBase =>
val isRegRefleshFlip = withClockAndReset( io.ides_pclk.asClock, reset ){ RegInit(false.B) }
val wrRegAddr = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(10.W)) }
val wrRegData = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(16.W)) }
withClockAndReset( io.ides_pclk.asClock, reset ){//100M
mirrorDown.io.clockw := io.ides_pclk.asBool
mirrorUp.io.clockr := io.ides_pclk.asBool
val fsmcCSSync = ShiftRegisters( io.FSMC.cs, 3, false.B, true.B )
val fsmcRDSync = ShiftRegisters( io.FSMC.rd, 3, false.B, true.B )
val fsmcWRSync = ShiftRegisters( io.FSMC.wr, 3, false.B, true.B )
val fsmcADVSync = ShiftRegisters( io.FSMC.adv, 3, false.B, true.B )
io.FSMC.ADOEn := fsmcRDSync(1)
val latchAddr = RegEnable( io.FSMC.ADIn, ~fsmcADVSync(2) & fsmcADVSync(1) )
val isAccessSRAM = ~latchAddr.extract(10)
val isAccessReg = latchAddr.extract(10)
val activeAddr = latchAddr(9,0)
val regOut = Wire(UInt(16.W))
val fsmcCSWRSync = ShiftRegisters( io.FSMC.cs & io.FSMC.wr, 3, false.B, true.B )
val fsmcCSRDSync = ShiftRegisters( io.FSMC.cs & io.FSMC.rd, 3, false.B, true.B )
// // val fsmcAddrSync = ShiftRegister( io.FSMC.addr, 2, 0.U, true.B )
// // val fsmcADInSync = ShiftRegister( io.FSMC.ADIn, 2, 0.U, true.B )
// val fsmcCSnSync = ShiftRegister( io.FSMC.csn, 2, true.B, true.B )
// val fsmcRDnSync = ShiftRegister( io.FSMC.rdn, 2, true.B, true.B )
// val fsmcWRnSync = ShiftRegister( io.FSMC.wrn, 2, true.B, true.B )
// val fsmcADVnSync = ShiftRegister( io.FSMC.advn, 2, true.B, true.B )
mirrorDown.io.enw := isAccessSRAM & ~fsmcCSWRSync(2) & fsmcCSWRSync(1)
mirrorDown.io.addrw := activeAddr
mirrorDown.io.dataw := io.FSMC.ADIn
mirrorUp.io.enr := isAccessSRAM & ~fsmcCSRDSync(2) & fsmcCSRDSync(1)
mirrorUp.io.addrr := activeAddr
io.FSMC.ADOut := Mux( isAccessReg, regOut, mirrorUp.io.datar)
regOut := Mux1H(Seq(
( activeAddr === 0.U) ->
Cat(
statusCDRErr ,
statusCRCErr ,
statusLinkErr,
statusSynch ,
statusInit
),
( activeAddr === 1.U) ->
Cat(
ctrlTransmit,
0.U(1.W),
0.U(1.W),
0.U(1.W),
ctrlSynch,
ctrlInit
),
( activeAddr === 2.U) -> slvNum,
( activeAddr === 3.U) -> slvOffLine,
))
when( isAccessReg & ~fsmcCSWRSync(2) & fsmcCSWRSync(1) ){
// io.FSMC.ADOEn := fsmcRDnSync
// val latchAddr = RegEnable( io.FSMC.ADIn, ~fsmcADVnSync )
isRegRefleshFlip := ~isRegRefleshFlip
wrRegAddr := activeAddr
wrRegData := io.FSMC.ADIn
// val isAccessSRAM = ~latchAddr.extract(9)
// val isAccessReg = latchAddr.extract(9)
// val activeAddr = latchAddr(8,0)
// val regOut = Wire(UInt(16.W))
// mirrorDown.io.enw := isAccessSRAM & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.wrn, 2, false.B, true.B )
// mirrorDown.io.addrw := activeAddr
// mirrorDown.io.dataw := io.FSMC.ADIn
// mirrorUp.io.enr := isAccessSRAM & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.rdn, 2, false.B, true.B )
// mirrorUp.io.addrr := activeAddr
}
// io.FSMC.ADOut := Mux( isAccessReg, regOut, mirrorUp.io.datar)
// regOut := Mux1H(Seq(
// ( activeAddr === 0.U) ->
// Cat(
// statusCDRErr ,
// statusCRCErr ,
// statusLinkErr,
// statusSynch ,
// statusInit
// ),
// ( activeAddr === 1.U) ->
// Cat(
// ctrlTransmit,
// 0.U(1.W),
// 0.U(1.W),
// 0.U(1.W),
// ctrlSynch,
// ctrlInit
// ),
// ( activeAddr === 2.U) -> slvNum,
// ( activeAddr === 3.U) -> slvOffLine,
// ))
// // when( isAccessReg & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.wrn, 2, false.B, true.B ) & ( activeAddr === 0.U) ){
// // status := io.FSMC.ADIn
// // }
// when( isAccessReg & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.wrn, 2, false.B, true.B ) & ( activeAddr === 1.U) ){
// ctrlTransmit := io.FSMC.ADIn.extract(5)
// when( io.FSMC.ADIn.extract(4) ){
// statusCDRErr := false.B
// }
// when( io.FSMC.ADIn.extract(3) ){
// statusCRCErr := false.B
// }
// when( io.FSMC.ADIn.extract(2) ){
// statusLinkErr := false.B
// }
// ctrlSynch := io.FSMC.ADIn.extract(1)
// ctrlInit := io.FSMC.ADIn.extract(0)
// }
// // when( (isAccessReg & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.wrn, 2, false.B, true.B ) ) & ( activeAddr === 2.U) ){
// // slvNum := io.FSMC.ADIn
// // }
// when( (isAccessReg & ShiftRegister( ~io.FSMC.csn & ~io.FSMC.wrn, 2, false.B, true.B ) ) & ( activeAddr === 3.U) ){
// slvOffLine := io.FSMC.ADIn
// }
// }
trait BackBoardMstSim{ this: BackBoardMstLVDSBase =>
val ( powerUpCnt, isPowerUpTimeout ) = Counter(Range( 0,5200), ~ctrlInit & ~statusInit, false.B)
when( powerUpCnt === 500.U ){
ctrlInit := true.B
}
ctrlTransmit := statusInit
//10M
val isChkRegReflesh = RegInit(false.B)
when( isChkRegReflesh =/= isRegRefleshFlip ){
when( wrRegAddr === 1.U ){
ctrlTransmit := wrRegData.extract(5)
when( wrRegData.extract(4) ){
statusCDRErr := false.B
}
when( wrRegData.extract(3) ){
statusCRCErr := false.B
}
when( wrRegData.extract(2) ){
statusLinkErr := false.B
}
ctrlSynch := wrRegData.extract(1)
ctrlInit := wrRegData.extract(0)
}
}
}
// trait BackBoardMstSim{ this: BackBoardMstLVDSBase =>
// val ( powerUpCnt, isPowerUpTimeout ) = Counter(Range( 0,5200), ~ctrlInit & ~statusInit, false.B)
// when( powerUpCnt === 500.U ){
// ctrlInit := true.B
// }
// ctrlTransmit := statusInit
mirrorDown.io.enw := true.B
mirrorDown.io.addrw := powerUpCnt
mirrorDown.io.dataw := "h5555".U
// mirrorDown.io.enw := true.B
// mirrorDown.io.addrw := powerUpCnt
// mirrorDown.io.dataw := "h5555".U
mirrorUp.io.enr := false.B
mirrorUp.io.addrr := 0.U
// mirrorUp.io.enr := false.B
// mirrorUp.io.addrr := 0.U
val testDone = RegInit(false.B)
val testFail = RegInit(false.B)
io.testDone := ~testDone
io.testFail := ~testFail
}
// val testDone = RegInit(false.B)
// val testFail = RegInit(false.B)
// io.testDone := ~testDone
// io.testFail := ~testFail
// }
abstract class BackBoardMstLVDSBase extends BackBoardMstBase
// with BackBoardMstFSMC
with BackBoardMstSim
with BackBoardMstFSMC
// with BackBoardMstSim
{
@@ -269,7 +276,7 @@ trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>
frame_info_update_en := true.B
slave_type_num := Cat( "b00".U(2.W), slvNum )
slave_data_length := ((8/8)*16-1).U
slave_data_length := ((8/8)*32-1).U
tx_start := false.B
} .elsewhen( stateCur === 1.U ){ // tx start
@@ -301,7 +308,7 @@ trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>
frame_info_update_en := true.B
slave_type_num := Cat( "b00".U(2.W), slvNum )
slave_data_length := ((8/8)*16-1).U
slave_data_length := ((8/8)*32-1).U
tx_start := false.B
} .elsewhen( stateCur === 5.U ){ // tx start
@@ -317,11 +324,11 @@ trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>
when( lvdsMst.io.slave_link_num_valid ){
when( slvNum === lvdsMst.io.slave_link_num - 1.U ){
stateCur := 7.U
testDone := true.B
testFail := false.B
// testDone := true.B
// testFail := false.B
} .otherwise{
testDone := false.B
testFail := true.B
// testDone := false.B
// testFail := true.B
printf("Initialization failed, waitting for timeout!\n")
}
}
@@ -349,7 +356,7 @@ trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>
frame_info_update_en := true.B
slave_type_num := Cat( "b01".U(2.W), slvNum )
slave_data_length := ((8/8)*16-1).U
slave_data_length := ((8/8)*32-1).U
tx_start := false.B
} .elsewhen( stateCur === 10.U ){ // tx start
@@ -394,9 +401,9 @@ trait BackBoardMstLVDSInitialization{ this: BackBoardMstLVDSBase =>
trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
val trigger = ctrlTransmit & ~RegNext(ctrlTransmit, false.B)
val ( _, trigger ) = Counter(Range( 0,1000), ctrlTransmit )
// val ( _, trigger ) = Counter(Range( 0,1000), ctrlTransmit )
when(ctrlTransmit){
when( trigger ){ //reset
@@ -414,7 +421,7 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
frame_info_update_en := true.B
slave_type_num := Cat( "b10".U(2.W), slvNum )
slave_data_length := ((8/8)*16-1).U
slave_data_length := ((8/8)*32-1).U
tx_start := false.B
} .elsewhen( stateCur === 1.U ){ // tx start
@@ -432,15 +439,15 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
}
} .elsewhen( stateCur === 3.U ){
ctrlTransmit := false.B
} .otherwise{
}
}
val addrr = RegInit(0.U(10.W))
val addrw = RegInit(0.U(10.W))
val addrr = RegInit(0.U(11.W))
val addrw = RegInit(0.U(11.W))
when( trigger ){
addrw := 0.U