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FSMC跑测试

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This commit is contained in:
RuigeLee
2024-01-09 17:48:23 +08:00
parent d74a4754a7
commit d729dfbe7e
3 changed files with 74 additions and 47 deletions
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34
src/main/scala/backBoard/BackBoardMst.scala
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@@ -109,13 +109,13 @@ class BackBoardMstBase extends Module{ //10M
trait BackBoardMstFSMC{ this: BackBoardMstBase =>
val isRegRefleshFlip = withClockAndReset( io.ides_pclk.asClock, reset ){ RegInit(false.B) }
val wrRegAddr = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(10.W)) }
val wrRegData = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(16.W)) }
val isRegRefleshFlip = withClockAndReset( io.ides_pclk.asClock, reset ){ RegInit(false.B) } //100M
val wrRegAddr = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(10.W)) } //100M
val wrRegData = withClockAndReset( io.ides_pclk.asClock, reset ){ Reg(UInt(16.W)) } //100M
withClockAndReset( io.ides_pclk.asClock, reset ){//100M
mirrorDown.io.clockw := io.ides_pclk.asBool
mirrorUp.io.clockr := io.ides_pclk.asBool
mirrorDown.io.clockw := io.ides_pclk.asBool //100M
mirrorUp.io.clockr := io.ides_pclk.asBool //100M
val fsmcCSSync = ShiftRegisters( io.FSMC.cs, 3, false.B, true.B )
val fsmcRDSync = ShiftRegisters( io.FSMC.rd, 3, false.B, true.B )
@@ -137,6 +137,7 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
mirrorDown.io.enw := isAccessSRAM & ~fsmcCSWRSync(2) & fsmcCSWRSync(1)
mirrorDown.io.addrw := activeAddr
mirrorDown.io.dataw := io.FSMC.ADIn
@@ -188,9 +189,9 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
val isChkRegReflesh = RegInit(false.B)
when( isChkRegReflesh =/= isRegRefleshFlip ){
when( wrRegAddr === 1.U ){
ctrlTransmit := wrRegData.extract(5)
isChkRegReflesh := ~isChkRegReflesh
when( wrRegAddr === 0.U ){
when( wrRegData.extract(4) ){
statusCDRErr := false.B
}
@@ -200,9 +201,22 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
when( wrRegData.extract(2) ){
statusLinkErr := false.B
}
}
when( wrRegAddr === 1.U ){
ctrlTransmit := wrRegData.extract(5)
ctrlSynch := wrRegData.extract(1)
ctrlInit := wrRegData.extract(0)
when( wrRegData.extract(0) ){
ctrlInit := true.B
statusSynch := false.B
statusInit := false.B
}
}
}
@@ -476,18 +490,14 @@ trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
when( lvdsMst.io.closed_loop_err ){
slvOffLine := lvdsMst.io.link_err_location(5,0)
statusLinkErr := true.B
statusSynch := false.B
statusInit := false.B
}
when( lvdsMst.io.upstream_cdr_err ){
statusCDRErr := true.B
ctrlTransmit := false.B
}
when( lvdsMst.io.upstream_crc_valid & lvdsMst.io.upstream_crc_err ){
statusCRCErr := true.B
ctrlTransmit := false.B
}
}