diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 7fe74d6..8307909 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -110,12 +110,12 @@ trait CDRInMultiSample{ this: CDRInBase =>
       (sampleReg_sync(i+0) & sampleReg_sync(i+1))
     }
 
-  val clearCnt = Reg(UInt(4.W))
+  val clearCnt = Reg(UInt(3.W))
   val arbLock = Reg(UInt( clkNum.W ))
   val isLock = RegInit(false.B)
 
   when( sampleReg.reduce(_|_) === false.B ){
-    when( clearCnt =/= 10.U ){
+    when( clearCnt =/= 6.U ){
       clearCnt := clearCnt + 1.U
     }
   } .otherwise{
@@ -132,7 +132,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
         isLock := true.B
       }
     }
-  } .elsewhen( clearCnt === 10.U ){
+  } .elsewhen( clearCnt === 6.U ){
     isLock := false.B
   }
 
@@ -171,6 +171,7 @@ trait CDRInAxis{ this: CDRInBase =>
   val checkSFD = RegInit( 0.U(20.W) ); checkSFD := Cat( checkSFD(18,0), syncSerDat )
 
   val shiftData = Dualb4b5Decoder(checkSFD(9,0))
+  val isReleaseLock = checkSFD(9,0) === "b0000000010".U
 
   val payloadLen = RegInit(0.U(12.W))
   when( byteCnt === 0.U & bitCnt === 9.U & stateCurr === STATE_HEADER ){
@@ -206,8 +207,9 @@ trait CDRInAxis{ this: CDRInBase =>
     when( stateCurr === STATE_HEADER ){
       byteCnt := Mux( byteCnt =/= (HeaderByte-1).U, byteCnt + 1.U, 0.U )
       assert( byteCnt <= (HeaderByte-1).U )
+      assert(~isReleaseLock)
     } .elsewhen( stateCurr === STATE_PAYLOAD ){
-      byteCnt := Mux( byteCnt =/= (payloadLen+ (4-1).U), byteCnt + 1.U, 0.U )
+      byteCnt := Mux( byteCnt =/= (payloadLen+ (4-1).U), Mux( isReleaseLock, byteCnt, byteCnt + 1.U ), 0.U )
       assert( byteCnt <= ( payloadLen+ (4-1).U ) )
     }
   }
@@ -229,7 +231,7 @@ trait CDRInAxis{ this: CDRInBase =>
 
   when( io.axis.fire ){
     axis_valid := false.B
-  } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) ){
+  } .elsewhen( bitCnt === 9.U & ( stateCurr === STATE_HEADER | (stateCurr === STATE_PAYLOAD & ~isReleaseLock) )  ){
     axis_valid := true.B
   }
 
diff --git a/src/main/scala/backBoard/ebus/CDROut.scala b/src/main/scala/backBoard/ebus/CDROut.scala
index 48d8cf9..6dfb5c6 100644
--- a/src/main/scala/backBoard/ebus/CDROut.scala
+++ b/src/main/scala/backBoard/ebus/CDROut.scala
@@ -35,7 +35,7 @@ class CDROut extends Module{
 
 
   val bitCnt = Reg(UInt(4.W))
-  val byteCnt = Reg(UInt(3.W)) //payload dont need to count
+  val byteCnt = Reg(UInt(7.W)) //payload 计数用于插入解锁位
 
   val shiftData = RegInit(0.U(10.W))
 
@@ -47,7 +47,7 @@ class CDROut extends Module{
 
   io.serDat := shiftData.extract(9)
   io.axis.ready :=
-    bitCnt === 9.U & (
+    bitCnt === 9.U & ~byteCnt.andR & (
       (stateCurr === STATE_PREAMBLE & byteCnt === (PRE_NUM-1).U) |
       (stateCurr === STATE_PAYLOAD)
     )
@@ -71,7 +71,11 @@ class CDROut extends Module{
           ( byteCnt === (PRE_NUM-1).U ) -> Dualb4b5Encoder(io.axis.bits.tdata),
         ))
       } .elsewhen( stateCurr === STATE_PAYLOAD ){
-        shiftData := Dualb4b5Encoder(io.axis.bits.tdata)
+        when( byteCnt.andR ){//全1用于提示接收解锁
+          shiftData := "b0000000010".U
+        } .otherwise{
+          shiftData := Dualb4b5Encoder(io.axis.bits.tdata)
+        }
       }
     }
   }
@@ -87,7 +91,7 @@ class CDROut extends Module{
     }
   }
 
-  when( (stateCurr === STATE_IDLE) | (stateCurr === STATE_PAYLOAD) ){
+  when( (stateCurr === STATE_IDLE) ){
     byteCnt := 0.U
   } .elsewhen( bitCnt === 9.U ){
     byteCnt := byteCnt + 1.U