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Merge branch 'feature/clk3_shift_allow' into mp_eb_dev

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# Conflicts:
#	src/main/scala/backBoard/ebus/CDRIn.scala
#	tb/shinTest/ShinTopSpiTb.v
#	tb/shinTest/gen_pkt.py
#	tb/shinTest/testcase/base.py
#	tb/shinTest/testcase/environment.py
This commit is contained in:
RuigeLee
2025-09-05 16:01:52 +08:00
parent a21d6eaf54 7ec88aa3a7
commit d5523eaa46
61 changed files with 2510 additions and 605 deletions
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32
tb/shinTest/ShinTopSpiTb.v
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@@ -104,15 +104,28 @@ module ShinTopSpiTb(
reg _reset_deactive;
wire [(`ALL_DEV_NUM - 1):0] isSoftReset;
reg [(`ALL_DEV_NUM - 1):0] isSoftReset_reg;
generate
for( genvar i = 0; i < `ALL_DEV_NUM; i = i + 1 ) begin
always @(posedge clock or posedge reset) begin
if(reset) isSoftReset_reg[i] <= 1'b0;
else isSoftReset_reg[i] <= isSoftReset[i];
end
end
endgenerate
wire [`DEV_NUM:0] io_int_sig;
reg latch0;
reg latch1;
ShinTop s_ShinTop_Mst(
.clock(clock),
.reset(reset | isSoftReset[0]),
.reset(reset | isSoftReset_reg[0]),
.io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]),
@@ -167,7 +180,7 @@ ShinTop s_ShinTop_Mst(
`ifdef DEFINE_SLAVE_DEVICE
ShinTop s_ShinTop_slv0(
.clock(clock),
.reset(reset | isSoftReset[1]),
.reset(reset | isSoftReset_reg[1]),
.io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]),
@@ -218,7 +231,7 @@ ShinTop s_ShinTop_slv0(
ShinTop s_ShinTop_slv1(
.clock(clock),
.reset(reset | isSoftReset[2]),
.reset(reset | isSoftReset_reg[2]),
.io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]),
@@ -269,7 +282,7 @@ ShinTop s_ShinTop_slv1(
ShinTop s_ShinTop_slv2(
.clock(clock),
.reset(reset | isSoftReset[3]),
.reset(reset | isSoftReset_reg[3]),
.io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]),
@@ -320,7 +333,7 @@ ShinTop s_ShinTop_slv2(
ShinTop s_ShinTop_slv3(
.clock(clock),
.reset(reset | isSoftReset[4]),
.reset(reset | isSoftReset_reg[4]),
.io_multiCLK_0(multiCLK[0]),
.io_multiCLK_1(multiCLK[1]),
@@ -885,7 +898,7 @@ task f_write(input [31:0] logh, input [15:0] saddress, input [7:0] scmd, input [
end
endtask
task wait_comm_finished();
task wait_comm_finished(input [16:0] dev_idx);
begin:WAIT_COMM_FINISHED_CODE
real st;
integer is_run;
@@ -893,6 +906,7 @@ task wait_comm_finished();
st = $realtime;
is_run = 1;
`ifdef enable_wait_clear_int
txBuf[0] = 8'h00;
txBuf[1] = 8'h78;
txBuf[2] = `SPI_WRITE;
@@ -902,7 +916,7 @@ task wait_comm_finished();
txBuf[6] = 8'h00;
length = 8'h07;
idx = `IF_IQSPI(0);
idx = `IF_IQSPI(dev_idx);
#500000
@(negedge sck)
@@ -914,7 +928,7 @@ task wait_comm_finished();
begin
end
`endif
while (is_run == 1) begin
txBuf[0] = 8'h00;
@@ -922,7 +936,7 @@ task wait_comm_finished();
txBuf[2] = `SPI_READ;
length = 8'h07;
idx = `IF_IQSPI(0);
idx = `IF_IQSPI(dev_idx);
#500000
@(negedge sck)