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Merge branch 'feature/clk3_shift_allow' into mp_eb_dev

Browse Source 
# Conflicts:
#	src/main/scala/backBoard/ebus/CDRIn.scala
#	tb/shinTest/ShinTopSpiTb.v
#	tb/shinTest/gen_pkt.py
#	tb/shinTest/testcase/base.py
#	tb/shinTest/testcase/environment.py
This commit is contained in:
RuigeLee
2025-09-05 16:01:52 +08:00
parent a21d6eaf54 7ec88aa3a7
commit d5523eaa46
61 changed files with 2510 additions and 605 deletions
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41
src/main/scala/backBoard/ebus/CDRIn.scala
View File

@@ -4,19 +4,24 @@ import chisel3._
import chisel3.util._
//work in 100MHZ
class CDRInIO extends Bundle{
val axis = Decoupled(new AXIS_Bundle(8))
val decode = Flipped(new Decode_Bundle)
val serDat = Input(Bool())
val flush = Input(Bool())
}
abstract class CDRInBase extends Module with RequireAsyncReset{
val io: CDRInIO = IO(new CDRInIO)
io.decode.dataIn := 0.U
val syncSerDat = Wire(Bool())
}
@@ -36,7 +41,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
dontTouch(sampleReg)
for( i <- 0 until clkNum ) {
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2, false.B, true.B ) }
}
val sampleReg_sync = for( i <- 0 until clkNum ) yield {
@@ -91,9 +96,9 @@ trait CDRInMultiSample{ this: CDRInBase =>
}
for( i <- 0 until (8*clkNum)-2 ) {dontTouch(flitReg(i))}
val clearCnt = Reg(UInt(4.W))
val checkCnt = Reg(UInt(4.W))
val arbCali = Reg(UInt( (log2Ceil(8*clkNum)).W ))
val clearCnt = RegInit(0.U(4.W))
val checkCnt = RegInit(0.U(4.W))
val arbCali = RegInit(0.U( (log2Ceil(2*clkNum)).W ))
val isLock = RegInit(false.B)
when( (7*clkNum until 8*clkNum).map{ i => sampleReg_Align(i)}.reduce(_|_) === false.B ){
@@ -201,8 +206,8 @@ trait CDRInAxis{ this: CDRInBase =>
def HeaderByte: Int = 4
val ETH_PRE = "b1100010001".U(10.W)
val ETH_SFD = "b0110100111".U(10.W)
val ETH_PRE = "h68".U(8.W)
val ETH_SFD = "h25".U(8.W)
val STATE_IDLE = 0.U
val STATE_HEADER = 1.U
@@ -211,18 +216,20 @@ trait CDRInAxis{ this: CDRInBase =>
val stateNext = Wire(UInt(2.W))
val stateCurr = RegNext( stateNext, STATE_IDLE )
val bitCnt = Reg(UInt(4.W))
val bitCnt = RegInit(0.U(4.W))
val byteCnt = RegInit(0.U((12+1).W))
val checkSFD = RegInit( 0.U(20.W) )
val checkSFD = RegInit( 0.U(10.W) )
when( io.flush ){
checkSFD := 0.U
} .otherwise{
checkSFD := Cat( checkSFD(18,0), syncSerDat )
checkSFD := Cat( checkSFD(8,0), syncSerDat )
}
val shiftData = Dualb4b5Decoder(checkSFD(9,0))
io.decode.dataIn := checkSFD(9,0)
val shiftData = io.decode.dataOut
val shiftData10Next = ShiftRegister( shiftData, 10, 0.U(8.W), true.B )
val payloadLen = RegInit(0.U(12.W))
@@ -237,7 +244,7 @@ trait CDRInAxis{ this: CDRInBase =>
stateNext :=
Mux( io.flush, STATE_IDLE,
Mux1H(Seq(
(stateCurr === STATE_IDLE) -> ( Mux( checkSFD === Cat(ETH_PRE , ETH_SFD), STATE_HEADER, STATE_IDLE )), //IDLE
(stateCurr === STATE_IDLE) -> ( Mux( shiftData10Next === ETH_PRE && shiftData === ETH_SFD , STATE_HEADER, STATE_IDLE )), //IDLE
(stateCurr === STATE_HEADER) -> ( Mux( (byteCnt === (HeaderByte-1).U) & (bitCnt === 9.U), STATE_PAYLOAD, STATE_HEADER ) ),
(stateCurr === STATE_PAYLOAD) -> ( Mux( (byteCnt === (payloadLen + (4 - 1).U) ) & (bitCnt === 9.U), STATE_IDLE, STATE_PAYLOAD )), // PAYLOAD
)) //crc
@@ -247,7 +254,7 @@ trait CDRInAxis{ this: CDRInBase =>
when( stateCurr === STATE_IDLE & ( checkSFD === Cat(ETH_PRE, ETH_SFD) ) ){ //first align
when( stateCurr === STATE_IDLE & ( shiftData10Next === ETH_PRE && shiftData === ETH_SFD ) ){ //first align
bitCnt := 0.U
} .otherwise{
when( bitCnt === 9.U ){
@@ -259,7 +266,7 @@ trait CDRInAxis{ this: CDRInBase =>
when( io.flush ){
byteCnt := 0.U
} .elsewhen( stateCurr === STATE_IDLE & ( checkSFD === Cat(ETH_PRE, ETH_SFD) ) ){ //first align
} .elsewhen( stateCurr === STATE_IDLE & ( shiftData10Next === ETH_PRE && shiftData === ETH_SFD ) ){ //first align
byteCnt := 0.U
} .elsewhen( bitCnt === 9.U ){
when( stateCurr === STATE_HEADER ){
@@ -276,7 +283,7 @@ trait CDRInAxis{ this: CDRInBase =>
val axis_valid = RegInit(false.B)
val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
val axis_tdata = RegEnable( shiftData, 0.U(8.W), bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
val axis_tuser = false.B
val axis_tlast = RegInit( false.B )

34
src/main/scala/backBoard/ebus/CDROut.scala
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@@ -9,14 +9,20 @@ class AXIS_Bundle(dw: Int) extends Bundle{
val tuser = Bool()
}
//work in 100MHZ
class CDROutIO extends Bundle{
val axis = Flipped(Decoupled(new AXIS_Bundle(8)))
val axis = Flipped(Decoupled(new AXIS_Bundle(8)))
val encode = Flipped(new Encode_Bundle)
val serDat = Output(Bool())
val flush = Input(Bool())
}
@@ -29,17 +35,19 @@ class CDROut extends Module with RequireAsyncReset{
def STATE_PREAMBLE = 1.U
def STATE_PAYLOAD = 2.U
val ETH_PRE = "b1100010001".U(10.W)
val ETH_SFD = "b0110100111".U(10.W)
val ETH_PRE = "h68".U(8.W)
val ETH_SFD = "h25".U(8.W)
val stateNext = Wire(UInt(2.W))
val stateCurr = RegNext( stateNext, 0.U )
val bitCnt = Reg(UInt(4.W))
val byteCnt = Reg(UInt(3.W)) //payload dont need to count
val bitCnt = RegInit(0.U(4.W))
val byteCnt = RegInit(0.U(3.W)) //payload dont need to count
val shiftData = RegInit(0.U(10.W))
io.encode.isEnable := false.B //组合逻辑
io.encode.dataIn := 0.U //组合逻辑
stateNext :=
Mux( io.flush, STATE_IDLE,
@@ -65,18 +73,24 @@ class CDROut extends Module with RequireAsyncReset{
when( io.flush ){
shiftData := 0.U
} .elsewhen( stateCurr === STATE_IDLE & stateNext === STATE_PREAMBLE){ //PRE
shiftData := ETH_PRE
shiftData := io.encode.dataOut
io.encode.dataIn := ETH_PRE //组合逻辑
io.encode.isEnable := true.B //组合逻辑
} .otherwise{
when( bitCnt =/= 9.U ){
shiftData := shiftData << 1
} .otherwise{ //bitCnt === 9.U
when( stateCurr === STATE_PREAMBLE ){
shiftData := MuxCase( ETH_PRE, Array(
shiftData := io.encode.dataOut
io.encode.dataIn := MuxCase( ETH_PRE, Array(
( byteCnt === (PRE_NUM-2).U ) -> ETH_SFD,
( byteCnt === (PRE_NUM-1).U ) -> Dualb4b5Encoder(io.axis.bits.tdata),
))
( byteCnt === (PRE_NUM-1).U ) -> io.axis.bits.tdata,
)) //组合逻辑
io.encode.isEnable := true.B //组合逻辑
} .elsewhen( stateCurr === STATE_PAYLOAD ){
shiftData := Dualb4b5Encoder(io.axis.bits.tdata)
io.encode.dataIn := io.axis.bits.tdata //组合逻辑
shiftData := io.encode.dataOut
io.encode.isEnable := true.B //组合逻辑
}
}
}

2
src/main/scala/backBoard/ebus/Encryptor.scala
View File

@@ -13,7 +13,7 @@ class Encryptor_IO_Bundle extends Bundle{
class Encryptor extends Module{
val io: Encryptor_IO_Bundle = IO(new Encryptor_IO_Bundle)
val encryptReg = Reg(UInt(128.W))
val encryptReg = RegInit(0.U(128.W))
when( io.init.valid ){
encryptReg := io.init.bits

13
src/main/scala/backBoard/ebus/b4b5.scala
View File

@@ -63,3 +63,16 @@ object Dualb4b5Decoder{
Cat( b4b5Decoder(enq(9,5)), b4b5Decoder(enq(4,0)) )
}
}
class b4b5DualEncode extends Module with RequireAsyncReset{
val io = IO(new Encode_Bundle)
io.dataOut := Dualb4b5Encoder(io.dataIn)
}
class b4b5DualDecode extends Module with RequireAsyncReset{
val io = IO(new Decode_Bundle)
io.dataOut := Dualb4b5Decoder(io.dataIn)
}

190
src/main/scala/backBoard/ebus/b8b10.scala Normal file
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@@ -0,0 +1,190 @@
package BACK
import chisel3._
import chisel3.util._
class Encode_Bundle extends Bundle{
val dataIn = Input(UInt(8.W))
val isEnable = Input(Bool())
val dataOut = Output(UInt(10.W))
}
class Decode_Bundle extends Bundle{
val dataIn = Input(UInt(10.W))
val dataOut = Output(UInt(8.W))
}
class b8b10Encode extends Module with RequireAsyncReset{
val io = IO(new Encode_Bundle)
val rd = RegInit(false.B)
val b5b6LookUp = Mux1H(Seq(
(io.dataIn(4,0) === "b00000".U) -> Mux( ~rd, "b100111".U(6.W), "b011000".U(6.W) ),
(io.dataIn(4,0) === "b00001".U) -> Mux( ~rd, "b011101".U(6.W), "b100010".U(6.W) ),
(io.dataIn(4,0) === "b00010".U) -> Mux( ~rd, "b101101".U(6.W), "b010010".U(6.W) ),
(io.dataIn(4,0) === "b00011".U) -> "b110001".U(6.W),
(io.dataIn(4,0) === "b00100".U) -> Mux( ~rd, "b110101".U(6.W), "b001010".U(6.W) ),
(io.dataIn(4,0) === "b00101".U) -> "b101001".U(6.W),
(io.dataIn(4,0) === "b00110".U) -> "b011001".U(6.W),
(io.dataIn(4,0) === "b00111".U) -> Mux( ~rd, "b111000".U(6.W), "b000111".U(6.W) ),
(io.dataIn(4,0) === "b01000".U) -> Mux( ~rd, "b111001".U(6.W), "b000110".U(6.W) ),
(io.dataIn(4,0) === "b01001".U) -> "b100101".U(6.W),
(io.dataIn(4,0) === "b01010".U) -> "b010101".U(6.W),
(io.dataIn(4,0) === "b01011".U) -> "b110100".U(6.W),
(io.dataIn(4,0) === "b01100".U) -> "b001101".U(6.W),
(io.dataIn(4,0) === "b01101".U) -> "b101100".U(6.W),
(io.dataIn(4,0) === "b01110".U) -> "b011100".U(6.W),
(io.dataIn(4,0) === "b01111".U) -> Mux( ~rd, "b010111".U(6.W), "b101000".U(6.W) ),
(io.dataIn(4,0) === "b10000".U) -> Mux( ~rd, "b011011".U(6.W), "b100100".U(6.W) ),
(io.dataIn(4,0) === "b10001".U) -> "b100011".U(6.W),
(io.dataIn(4,0) === "b10010".U) -> "b010011".U(6.W),
(io.dataIn(4,0) === "b10011".U) -> "b110010".U(6.W),
(io.dataIn(4,0) === "b10100".U) -> "b001011".U(6.W),
(io.dataIn(4,0) === "b10101".U) -> "b101010".U(6.W),
(io.dataIn(4,0) === "b10110".U) -> "b011010".U(6.W),
(io.dataIn(4,0) === "b10111".U) -> Mux( ~rd, "b111010".U(6.W), "b000101".U(6.W) ),
(io.dataIn(4,0) === "b11000".U) -> Mux( ~rd, "b110011".U(6.W), "b001100".U(6.W) ),
(io.dataIn(4,0) === "b11001".U) -> "b100110".U(6.W),
(io.dataIn(4,0) === "b11010".U) -> "b010110".U(6.W),
(io.dataIn(4,0) === "b11011".U) -> Mux( ~rd, "b110110".U(6.W), "b001001".U(6.W) ),
(io.dataIn(4,0) === "b11100".U) -> "b001110".U(6.W),
(io.dataIn(4,0) === "b11101".U) -> Mux( ~rd, "b101110".U(6.W), "b010001".U(6.W) ),
(io.dataIn(4,0) === "b11110".U) -> Mux( ~rd, "b011110".U(6.W), "b100001".U(6.W) ),
(io.dataIn(4,0) === "b11111".U) -> Mux( ~rd, "b101011".U(6.W), "b010100".U(6.W) )
))
val b5b6RD = Mux1H(Seq(
(io.dataIn(4,0) === "b00000".U) -> ~rd,
(io.dataIn(4,0) === "b00001".U) -> ~rd,
(io.dataIn(4,0) === "b00010".U) -> ~rd,
(io.dataIn(4,0) === "b00011".U) -> rd,
(io.dataIn(4,0) === "b00100".U) -> ~rd,
(io.dataIn(4,0) === "b00101".U) -> rd,
(io.dataIn(4,0) === "b00110".U) -> rd,
(io.dataIn(4,0) === "b00111".U) -> rd,
(io.dataIn(4,0) === "b01000".U) -> ~rd,
(io.dataIn(4,0) === "b01001".U) -> rd,
(io.dataIn(4,0) === "b01010".U) -> rd,
(io.dataIn(4,0) === "b01011".U) -> rd,
(io.dataIn(4,0) === "b01100".U) -> rd,
(io.dataIn(4,0) === "b01101".U) -> rd,
(io.dataIn(4,0) === "b01110".U) -> rd,
(io.dataIn(4,0) === "b01111".U) -> ~rd,
(io.dataIn(4,0) === "b10000".U) -> ~rd,
(io.dataIn(4,0) === "b10001".U) -> rd,
(io.dataIn(4,0) === "b10010".U) -> rd,
(io.dataIn(4,0) === "b10011".U) -> rd,
(io.dataIn(4,0) === "b10100".U) -> rd,
(io.dataIn(4,0) === "b10101".U) -> rd,
(io.dataIn(4,0) === "b10110".U) -> rd,
(io.dataIn(4,0) === "b10111".U) -> ~rd,
(io.dataIn(4,0) === "b11000".U) -> ~rd,
(io.dataIn(4,0) === "b11001".U) -> rd,
(io.dataIn(4,0) === "b11010".U) -> rd,
(io.dataIn(4,0) === "b11011".U) -> ~rd,
(io.dataIn(4,0) === "b11100".U) -> rd,
(io.dataIn(4,0) === "b11101".U) -> ~rd,
(io.dataIn(4,0) === "b11110".U) -> ~rd,
(io.dataIn(4,0) === "b11111".U) -> ~rd,
))
val b3b4LookUp = Mux1H(Seq(
(io.dataIn(7,5) === "b000".U) -> Mux( ~b5b6RD, "b1011".U(4.W), "b0100".U(4.W) ),
(io.dataIn(7,5) === "b001".U) -> "b1001".U(4.W),
(io.dataIn(7,5) === "b010".U) -> "b0101".U(4.W),
(io.dataIn(7,5) === "b011".U) -> Mux( ~b5b6RD, "b1100".U(4.W), "b0011".U(4.W) ),
(io.dataIn(7,5) === "b100".U) -> Mux( ~b5b6RD, "b1101".U(4.W), "b0010".U(4.W) ),
(io.dataIn(7,5) === "b101".U) -> "b1010".U(4.W),
(io.dataIn(7,5) === "b110".U) -> "b0110".U(4.W),
(io.dataIn(7,5) === "b111".U) -> MuxCase( Mux( ~b5b6RD, "b1110".U(4.W), "b0001".U(4.W) ), Array(
((io.dataIn(4,0) === 17.U || io.dataIn(4,0) === 18.U || io.dataIn(4,0) === 20.U) & ~b5b6RD) -> "b0111".U(4.W), // 17, 18, 20 are special cases
((io.dataIn(4,0) === 11.U || io.dataIn(4,0) === 13.U || io.dataIn(4,0) === 14.U) & b5b6RD) -> "b1000".U(4.W), // 11, 13, 14 are special cases
))
))
val b3b4RD = Mux1H(Seq(
(io.dataIn(7,5) === "b000".U) -> ~b5b6RD,
(io.dataIn(7,5) === "b001".U) -> b5b6RD,
(io.dataIn(7,5) === "b010".U) -> b5b6RD,
(io.dataIn(7,5) === "b011".U) -> b5b6RD,
(io.dataIn(7,5) === "b100".U) -> ~b5b6RD,
(io.dataIn(7,5) === "b101".U) -> b5b6RD,
(io.dataIn(7,5) === "b110".U) -> b5b6RD,
(io.dataIn(7,5) === "b111".U) -> ~b5b6RD,
))
io.dataOut := Cat(b5b6LookUp, b3b4LookUp)
when (io.isEnable) {
rd := b3b4RD
assert( io.dataOut(4,0) =/= 0.U && io.dataOut(4,0) =/= 31.U, "Invalid 8b10b encoding Output!")
assert( io.dataOut(5,1) =/= 0.U && io.dataOut(5,1) =/= 31.U, "Invalid 8b10b encoding Output!")
assert( io.dataOut(6,2) =/= 0.U && io.dataOut(6,2) =/= 31.U, "Invalid 8b10b encoding Output!")
assert( io.dataOut(7,3) =/= 0.U && io.dataOut(7,3) =/= 31.U, "Invalid 8b10b encoding Output!")
assert( io.dataOut(8,4) =/= 0.U && io.dataOut(8,4) =/= 31.U, "Invalid 8b10b encoding Output!")
assert( io.dataOut(9,5) =/= 0.U && io.dataOut(9,5) =/= 31.U, "Invalid 8b10b encoding Output!")
}
}
class b8b10Decode extends Module with RequireAsyncReset{
val io = IO(new Decode_Bundle)
val b5b6LookUp = Mux1H(Seq(
(io.dataIn(9,4) === "b100111".U(6.W) || io.dataIn(9,4) === "b011000".U(6.W) ) -> "b00000".U,
(io.dataIn(9,4) === "b011101".U(6.W) || io.dataIn(9,4) === "b100010".U(6.W) ) -> "b00001".U,
(io.dataIn(9,4) === "b101101".U(6.W) || io.dataIn(9,4) === "b010010".U(6.W) ) -> "b00010".U,
(io.dataIn(9,4) === "b110001".U(6.W)) -> "b00011".U,
(io.dataIn(9,4) === "b110101".U(6.W) || io.dataIn(9,4) === "b001010".U(6.W) ) -> "b00100".U,
(io.dataIn(9,4) === "b101001".U(6.W)) -> "b00101".U,
(io.dataIn(9,4) === "b011001".U(6.W)) -> "b00110".U,
(io.dataIn(9,4) === "b111000".U(6.W) || io.dataIn(9,4) === "b000111".U(6.W) ) -> "b00111".U,
(io.dataIn(9,4) === "b111001".U(6.W) || io.dataIn(9,4) === "b000110".U(6.W) ) -> "b01000".U,
(io.dataIn(9,4) === "b100101".U(6.W)) -> "b01001".U,
(io.dataIn(9,4) === "b010101".U(6.W)) -> "b01010".U,
(io.dataIn(9,4) === "b110100".U(6.W)) -> "b01011".U,
(io.dataIn(9,4) === "b001101".U(6.W)) -> "b01100".U,
(io.dataIn(9,4) === "b101100".U(6.W)) -> "b01101".U,
(io.dataIn(9,4) === "b011100".U(6.W)) -> "b01110".U,
(io.dataIn(9,4) === "b010111".U(6.W) || io.dataIn(9,4) === "b101000".U(6.W) ) -> "b01111".U,
(io.dataIn(9,4) === "b011011".U(6.W) || io.dataIn(9,4) === "b100100".U(6.W) ) -> "b10000".U,
(io.dataIn(9,4) === "b100011".U(6.W)) -> "b10001".U,
(io.dataIn(9,4) === "b010011".U(6.W)) -> "b10010".U,
(io.dataIn(9,4) === "b110010".U(6.W)) -> "b10011".U,
(io.dataIn(9,4) === "b001011".U(6.W)) -> "b10100".U,
(io.dataIn(9,4) === "b101010".U(6.W)) -> "b10101".U,
(io.dataIn(9,4) === "b011010".U(6.W)) -> "b10110".U,
(io.dataIn(9,4) === "b111010".U(6.W) || io.dataIn(9,4) === "b000101".U(6.W) ) -> "b10111".U,
(io.dataIn(9,4) === "b110011".U(6.W) || io.dataIn(9,4) === "b001100".U(6.W) ) -> "b11000".U,
(io.dataIn(9,4) === "b100110".U(6.W)) -> "b11001".U,
(io.dataIn(9,4) === "b010110".U(6.W)) -> "b11010".U,
(io.dataIn(9,4) === "b110110".U(6.W) || io.dataIn(9,4) === "b001001".U(6.W) ) -> "b11011".U,
(io.dataIn(9,4) === "b001110".U(6.W)) -> "b11100".U,
(io.dataIn(9,4) === "b101110".U(6.W) || io.dataIn(9,4) === "b010001".U(6.W) ) -> "b11101".U,
(io.dataIn(9,4) === "b011110".U(6.W) || io.dataIn(9,4) === "b100001".U(6.W) ) -> "b11110".U,
(io.dataIn(9,4) === "b101011".U(6.W) || io.dataIn(9,4) === "b010100".U(6.W) ) -> "b11111".U,
))
val b3b4LookUp = Mux1H(Seq(
(io.dataIn(3,0) === "b1011".U(4.W) || io.dataIn(3,0) === "b0100".U(4.W) ) -> "b000".U,
(io.dataIn(3,0) === "b1001".U(4.W)) -> "b001".U,
(io.dataIn(3,0) === "b0101".U(4.W)) -> "b010".U,
(io.dataIn(3,0) === "b1100".U(4.W) || io.dataIn(3,0) === "b0011".U(4.W) ) -> "b011".U,
(io.dataIn(3,0) === "b1101".U(4.W) || io.dataIn(3,0) === "b0010".U(4.W) ) -> "b100".U,
(io.dataIn(3,0) === "b1010".U(4.W)) -> "b101".U,
(io.dataIn(3,0) === "b0110".U(4.W)) -> "b110".U,
(io.dataIn(3,0) === "b1110".U(4.W) ||
io.dataIn(3,0) === "b0001".U(4.W) ||
io.dataIn(3,0) === "b0111".U(4.W) ||
io.dataIn(3,0) === "b1000".U(4.W)) -> "b111".U,
))
io.dataOut := Cat(b3b4LookUp, b5b6LookUp)
}