From d53d1dbe9b1f2c13b6f17c9b8523c717bb7c74c1 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Fri, 31 Jul 2026 16:48:27 +0800 Subject: [PATCH] =?UTF-8?q?*=20=E4=B8=8A=E4=B8=8B=E8=A1=8C=E6=B8=85?= =?UTF-8?q?=E7=A1=AC=E4=BB=B6=E9=94=99=E8=AF=AF=E7=9A=84=E6=9D=A1=E4=BB=B6?= =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E4=B8=BA**=E4=B8=8A**=E8=A1=8C=E6=8E=A5?= =?UTF-8?q?=E6=94=B6=E5=88=B0`isK28=5F0`=20*=20=E4=BB=8E=E7=AB=99=E5=8F=91?= =?UTF-8?q?=E7=94=9F=E7=A1=AC=E4=BB=B6=E9=94=99=E8=AF=AF=E6=97=B6=EF=BC=8C?= =?UTF-8?q?=E8=BD=AF=E4=BB=B6=E5=85=88=E5=86=99`clr`=E5=AF=84=E5=AD=98?= =?UTF-8?q?=E5=99=A8=E9=A2=84=E8=A7=A3=E9=94=81=EF=BC=8C=E5=85=B6=E5=90=8E?= =?UTF-8?q?=E4=B8=8A=E8=A1=8C=E6=96=B9=E5=90=91=E6=8E=A5=E6=94=B6=E5=88=B0?= =?UTF-8?q?K28=5F0=E5=AE=8C=E6=88=90=E6=AD=A3=E5=BC=8F=E8=A7=A3=E9=94=81?= =?UTF-8?q?=20*=20=E9=A2=84=E8=A7=A3=E9=94=81=E9=9C=80=E8=A6=81=E5=9C=A8K2?= =?UTF-8?q?8=5F0=E4=B9=8B=E5=89=8D=EF=BC=8C=E4=B8=A4=E8=80=85=E5=9C=A8?= =?UTF-8?q?=E5=90=8C=E4=B8=80=E6=8B=8D=E5=88=B0=E8=BE=BE=E5=B0=86=E5=8F=AA?= =?UTF-8?q?=E4=BC=9A=E4=BA=A7=E7=94=9F=E9=A2=84=E8=A7=A3=E9=94=81=E6=95=88?= =?UTF-8?q?=E6=9E=9C?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- doc/spec/物理层优化.md | 5 ++++ .../scala/backBoard/shin/MstSlvSwitch.scala | 28 +++++++++++++++---- 2 files changed, 27 insertions(+), 6 deletions(-) diff --git a/doc/spec/物理层优化.md b/doc/spec/物理层优化.md index eeabb5f..97434ff 100644 --- a/doc/spec/物理层优化.md +++ b/doc/spec/物理层优化.md @@ -48,6 +48,11 @@ - 上行relay在`isProbeAck`跳变状态直接拷贝下行寄存器信息，其它条件看上行输入的6个`isK`布尔信号直接转译8bit原始码 +* 上下行清硬件错误的条件增加为**上**行接收到`isK28_0` +* 从站发生硬件错误时，软件先写`clr`寄存器预解锁，其后上行方向接收到K28_0完成正式解锁 +* 预解锁需要在K28_0之前，两者在同一拍到达将只会产生预解锁效果 + + --------------------------------------- 以下是大模型补充区域 diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala index 1a0aa69..2b52960 100644 --- a/src/main/scala/backBoard/shin/MstSlvSwitch.scala +++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala @@ -435,12 +435,28 @@ trait MstSlvSwitchSlave{ this: MstSlvSwitchBase => } - slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) & interface.io.intHWClr(0) - slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1) & interface.io.intHWClr(1) - downCDRInAxis.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0), false.B ) - upCDRInAxis.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1), false.B ) - downCDROut.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0), false.B ) - upCDROut.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1), false.B ) + val intHWClr = for( _ <- 0 until 2) yield Wire(Bool()) + val intHWClrCMDRev = for( _ <- 0 until 2) yield RegInit(false.B) + + for( i <- 0 until 2 ){ + when( interface.io.intHWTrig(i) & interface.io.intHWClr(i) ){ + intHWClrCMDRev(i) := true.B + } .elsewhen( upCDRInAxis.io.isK28_0 ){ + intHWClrCMDRev(i) := false.B + } + + intHWClr(i) := intHWClrCMDRev(i) & upCDRInAxis.io.isK28_0 + } + + + + + slaveParser.io.intHWClr(0) := intHWClr(0) + slaveParser.io.intHWClr(1) := intHWClr(1) + downCDRInAxis.io.flush := RegNext( intHWClr(0), false.B ) + upCDRInAxis.io.flush := RegNext( intHWClr(1), false.B ) + downCDROut.io.flush := RegNext( intHWClr(0), false.B ) + upCDROut.io.flush := RegNext( intHWClr(1), false.B ) interface.io.lvds <> slaveParser.io.lvds