diff --git a/doc/spec/物理层优化.md b/doc/spec/物理层优化.md index eeabb5f..97434ff 100644 --- a/doc/spec/物理层优化.md +++ b/doc/spec/物理层优化.md @@ -48,6 +48,11 @@ - 上行relay在`isProbeAck`跳变状态直接拷贝下行寄存器信息,其它条件看上行输入的6个`isK`布尔信号直接转译8bit原始码 +* 上下行清硬件错误的条件增加为**上**行接收到`isK28_0` +* 从站发生硬件错误时,软件先写`clr`寄存器预解锁,其后上行方向接收到K28_0完成正式解锁 +* 预解锁需要在K28_0之前,两者在同一拍到达将只会产生预解锁效果 + + --------------------------------------- 以下是大模型补充区域 diff --git a/src/main/scala/backBoard/shin/MstSlvSwitch.scala b/src/main/scala/backBoard/shin/MstSlvSwitch.scala index 1a0aa69..2b52960 100644 --- a/src/main/scala/backBoard/shin/MstSlvSwitch.scala +++ b/src/main/scala/backBoard/shin/MstSlvSwitch.scala @@ -435,12 +435,28 @@ trait MstSlvSwitchSlave{ this: MstSlvSwitchBase => } - slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) & interface.io.intHWClr(0) - slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1) & interface.io.intHWClr(1) - downCDRInAxis.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0), false.B ) - upCDRInAxis.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1), false.B ) - downCDROut.io.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0), false.B ) - upCDROut.io.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1), false.B ) + val intHWClr = for( _ <- 0 until 2) yield Wire(Bool()) + val intHWClrCMDRev = for( _ <- 0 until 2) yield RegInit(false.B) + + for( i <- 0 until 2 ){ + when( interface.io.intHWTrig(i) & interface.io.intHWClr(i) ){ + intHWClrCMDRev(i) := true.B + } .elsewhen( upCDRInAxis.io.isK28_0 ){ + intHWClrCMDRev(i) := false.B + } + + intHWClr(i) := intHWClrCMDRev(i) & upCDRInAxis.io.isK28_0 + } + + + + + slaveParser.io.intHWClr(0) := intHWClr(0) + slaveParser.io.intHWClr(1) := intHWClr(1) + downCDRInAxis.io.flush := RegNext( intHWClr(0), false.B ) + upCDRInAxis.io.flush := RegNext( intHWClr(1), false.B ) + downCDROut.io.flush := RegNext( intHWClr(0), false.B ) + upCDROut.io.flush := RegNext( intHWClr(1), false.B ) interface.io.lvds <> slaveParser.io.lvds