From d3e456879524024db89e4db1b4cb030f3c732d66 Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Sun, 14 Apr 2024 20:15:56 +0800 Subject: [PATCH] =?UTF-8?q?=E9=AB=98=E5=BA=A6=E6=80=80=E7=96=91IO=E5=9C=A8?= =?UTF-8?q?=E9=AB=98=E9=A2=91=E7=8E=87=E4=B8=8B=E5=87=BA=E7=8E=B0=E4=BA=9A?= =?UTF-8?q?=E7=A8=B3=E6=80=81=E9=97=AE=E9=A2=98=EF=BC=8C=E5=AF=BC=E8=87=B4?= =?UTF-8?q?=E5=88=A4=E5=AE=9A=E6=9D=A1=E4=BB=B6=E4=B8=8D=E4=B8=80=E8=87=B4?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/LocalRegisters.scala | 230 ++++++++++-------- 1 file changed, 132 insertions(+), 98 deletions(-) diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala index 6565223..572e5b0 100644 --- a/src/main/scala/backBoard/LocalRegisters.scala +++ b/src/main/scala/backBoard/LocalRegisters.scala @@ -126,112 +126,147 @@ trait BackBoardSlvStatusPR { this: BackBoardSlvLocal => trait BackBoardSlvIn { this: BackBoardSlvLocal => - def gp: Int - val flitNum = 32 - require(flitNum <= 128) + // val flitNum = 32 + // require(flitNum <= 128) - val in = IO(Input(UInt((8*gp).W))) + val in = IO(Input(UInt(16.W))) - // val flitCnt = RegInit(MixedVecInit(Seq( 0.U(1.W), 0.U((log2Ceil(256/flitNum)).W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W)) )) - // val flitTrigger = Wire(Vec(9, Bool())) + val flitCnt = RegInit(MixedVecInit(Seq( 0.U(1.W), 0.U((log2Ceil(256/32)).W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W)) )) + val flitTrigger = Wire(Vec(9, Bool())) - // flitTrigger(0) := ~RegNext(flitTrigger(0)) + flitTrigger(0) := ~RegNext(flitTrigger(0)) - // flitTrigger(1) := flitCnt(1) >= (256/flitNum-1).U - // when( ~RegNext(usTrigger) & usTrigger ){ - // when( flitTrigger(1) ){ - // flitCnt(1) := 0.U - // } .otherwise{ - // flitCnt(1) := flitCnt(1) + 1.U - // } - - // } - - // flitTrigger(2) := flitCnt(2) === 1.U - // when( ~RegNext(flitTrigger(1)) & flitTrigger(1) ){ - // flitCnt(2) := flitCnt(2) + 1.U - // } - - // flitTrigger(3) := flitCnt(3) === 1.U - // when( ~RegNext(flitTrigger(2)) & flitTrigger(2) ){ - // flitCnt(3) := flitCnt(3) + 1.U - // } - - // flitTrigger(4) := flitCnt(4) === 1.U - // when( ~RegNext(flitTrigger(3)) & flitTrigger(3) ){ - // flitCnt(4) := flitCnt(4) + 1.U - // } - - // flitTrigger(5) := flitCnt(5) === 1.U - // when( ~RegNext(flitTrigger(4)) & flitTrigger(4) ){ - // flitCnt(5) := flitCnt(5) + 1.U - // } - - // flitTrigger(6) := flitCnt(6) === 1.U - // when( ~RegNext(flitTrigger(5)) & flitTrigger(5) ){ - // flitCnt(6) := flitCnt(6) + 1.U - // } - - // flitTrigger(7) := flitCnt(7) === 1.U - // when( ~RegNext(flitTrigger(6)) & flitTrigger(6) ){ - // flitCnt(7) := flitCnt(7) + 1.U - // } - - // flitTrigger(8) := flitCnt(8) === 1.U - // when( ~RegNext(flitTrigger(7)) & flitTrigger(7) ){ - // flitCnt(8) := flitCnt(8) + 1.U - // } - - for( j <- 0 until gp ) { - - // val digitalFilter = RegEnable( downReg(4+j), 1.U, statusPage === 0.U ) - - // val digitalIn = Reg( Vec(8, Bool()) ) - - when( statusPage === 0.U ){ - // upReg(2+j) := Cat( digitalIn.reverse ) - upReg(2+j) := in(8*j+7, 8*j) - upReg(4+j) := downReg(4+j) + flitTrigger(1) := flitCnt(1) >= (256/32-1).U + when( ~RegNext(usTrigger) & usTrigger ){ + when( flitTrigger(1) ){ + flitCnt(1) := 0.U + } .otherwise{ + flitCnt(1) := flitCnt(1) + 1.U } - - // for( i <- 0 until 8 ) { - - // val flitter = RegInit(VecInit( Seq.fill(flitNum){false.B})) - // val flitHi = RegInit(0.U((log2Ceil(flitNum+1)).W)) - - // ( 0 until 9 ).map{ k => - // when( digitalFilter === k.U ){ - // when( (if( k == 0 ){ true.B } else {~RegNext(flitTrigger(k)) & flitTrigger(k)}) ){ - // flitter(0) := in(i+8*j) - // (1 until flitNum).map{ k => - // flitter(k) := flitter(k-1) - // } - - // when( (~flitter(flitNum-1) & ~in(i+8*j)) | (flitter(flitNum-1) & in(i+8*j)) ){ - // flitHi := flitHi - // } .elsewhen( ~flitter(flitNum-1) & in(i+8*j) ){ - // flitHi := flitHi + 1.U - // } .elsewhen( flitter(flitNum-1) & ~in(i+8*j) ){ - // flitHi := flitHi - 1.U - // } - - // when( flitHi >= (flitNum*4/5).U ){ - // digitalIn(i) := true.B - // } .elsewhen( flitHi <= (flitNum/5).U ){ - // digitalIn(i) := false.B - // } - - // assert( flitHi <= flitNum.U ) - // assert( flitter.count( (k:Bool) => k === true.B ) === flitHi ) - - // } - // } - // } - // } } + flitTrigger(2) := flitCnt(2) === 1.U + when( ~RegNext(flitTrigger(1)) & flitTrigger(1) ){ + flitCnt(2) := flitCnt(2) + 1.U + } + + flitTrigger(3) := flitCnt(3) === 1.U + when( ~RegNext(flitTrigger(2)) & flitTrigger(2) ){ + flitCnt(3) := flitCnt(3) + 1.U + } + + flitTrigger(4) := flitCnt(4) === 1.U + when( ~RegNext(flitTrigger(3)) & flitTrigger(3) ){ + flitCnt(4) := flitCnt(4) + 1.U + } + + flitTrigger(5) := flitCnt(5) === 1.U + when( ~RegNext(flitTrigger(4)) & flitTrigger(4) ){ + flitCnt(5) := flitCnt(5) + 1.U + } + + flitTrigger(6) := flitCnt(6) === 1.U + when( ~RegNext(flitTrigger(5)) & flitTrigger(5) ){ + flitCnt(6) := flitCnt(6) + 1.U + } + + flitTrigger(7) := flitCnt(7) === 1.U + when( ~RegNext(flitTrigger(6)) & flitTrigger(6) ){ + flitCnt(7) := flitCnt(7) + 1.U + } + + flitTrigger(8) := flitCnt(8) === 1.U + when( ~RegNext(flitTrigger(7)) & flitTrigger(7) ){ + flitCnt(8) := flitCnt(8) + 1.U + } + + + val digitalFilter = for( i <- 0 until 2 ) yield RegEnable( downReg(4+i), 1.U, statusPage === 0.U ) + val digitalIn = Reg( Vec(16, Bool()) ) + + + val flitter = for( i <- 0 until 16 ) yield RegInit(VecInit( Seq.fill(32){false.B})) + val flitHi = for( i <- 0 until 16 ) yield RegInit(0.U((log2Ceil(32+1)).W)) + + + val temp0 = RegInit(0.U(8.W)) + val temp1 = RegInit(0.U(8.W)) + val temp2 = RegInit(0.U(8.W)) + val temp3 = RegInit(0.U(8.W)) + val temp4 = RegInit(0.U(8.W)) + val lock = RegInit(false.B) + + + when( statusPage === 0.U ){ + upReg(2) := Cat( ( 0 until 8 ).map{ i => digitalIn(i) }.reverse ) + upReg(3) := Cat( ( 8 until 16).map{ i => digitalIn(i) }.reverse ) + + upReg(4) := downReg(4) //digitalFilter + upReg(5) := downReg(5) + + upReg(16) := Cat( ( 0 until 8 ).map { i => flitter(1)(i) } ) + upReg(17) := Cat( ( 8 until 16 ).map{ i => flitter(1)(i) } ) + upReg(18) := Cat( ( 16 until 24 ).map{ i => flitter(1)(i) } ) + upReg(19) := Cat( ( 24 until 32 ).map{ i => flitter(1)(i) } ) + + upReg(20) := flitHi(1) + + + upReg(24) := temp0 + upReg(25) := temp1 + upReg(26) := temp2 + upReg(27) := temp3 + upReg(28) := temp4 + + + upReg(30) := in(7,0) + } + + + // for( i <- 0 until 16 ) { + for( i <- 0 until 8 ) { + // ( 0 until 9 ).map{ cfg => + when( true.B ) {//(if( i < 8 ) {digitalFilter(0) === cfg.U} else {digitalFilter(1) === cfg.U}) ){ + when( ~RegNext(flitTrigger(1)) & flitTrigger(1) ){//(if( cfg == 0 ){ true.B } else {~RegNext(flitTrigger(cfg)) & flitTrigger(cfg)}) ){ + flitter(i)(0) := in(i) + (1 until 32).map{ k => + flitter(i)(k) := flitter(i)(k-1) + } + + when( (~flitter(i)(31) & ~flitter(i)(0)) | (flitter(i)(31) & flitter(i)(0)) ){ + flitHi(i) := flitHi(i) + } .elsewhen( ~flitter(i)(31) & flitter(i)(0) ){ + flitHi(i) := flitHi(i) + 1.U + } .elsewhen( flitter(i)(31) & ~flitter(i)(0) ){ + flitHi(i) := flitHi(i) - 1.U + } + + when( flitHi(i) >= 26.U ){ + digitalIn(i) := true.B + } .elsewhen( flitHi(i) <= 6.U ){ + digitalIn(i) := false.B + } + + when( flitHi(i) > 32.U & ~lock ){ + lock := true.B + temp0 := Cat( ( 0 until 8 ).map { i => flitter(1)(i) } ) + temp1 := Cat( ( 8 until 16 ).map{ i => flitter(1)(i) } ) + temp2 := Cat( ( 16 until 24 ).map{ i => flitter(1)(i) } ) + temp3 := Cat( ( 24 until 32 ).map{ i => flitter(1)(i) } ) + + temp4 := flitHi(1) + } + + // assert( flitHi(i) <= 32.U ) + // assert( flitter(i).count( (k:Bool) => k === true.B ) === flitHi(i) ) + + } + } + // } + } + } @@ -240,7 +275,6 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal => class DIn16 extends BackBoardSlvLocal with BackBoardSlvStatusPR with BackBoardSlvIn{ - def gp = 2 }