diff --git a/src/main/scala/backBoard/LocalRegisters.scala b/src/main/scala/backBoard/LocalRegisters.scala
index 8c52d3b..9a5c64a 100644
--- a/src/main/scala/backBoard/LocalRegisters.scala
+++ b/src/main/scala/backBoard/LocalRegisters.scala
@@ -8,7 +8,6 @@ class ManualParamBundle extends Bundle{
   val moduleID = UInt( 16.W )
   val hwVersion = UInt( 16.W )
   val swVersion = UInt( 16.W )
-  // val batchID  = UInt( 16.W )
   val serial   = UInt( 48.W )
 }
 
@@ -24,7 +23,7 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
   val statusER   = RegInit(false.B)
   val statusLE   = RegInit(false.B)
   val statusSync = RegEnable( downRegTemp(1).extract(3).asBool, false.B, isCrcPass )
-  val statusNone = ~io.isLast
+  val statusNone = ~ShiftRegister(io.isLast, 2) 
 
 
 
@@ -50,9 +49,6 @@ abstract class BackBoardSlvLocal extends BackBoardSlvBase with BackBoardSlvDown
     upReg(12) := param.swVersion(7,0)
     upReg(13) := param.swVersion(15,8)
 
-    // upReg(15) := param.batchID(7,0)
-    // upReg(16) := param.batchID(15,8)
-
     upReg(14) := param.serial(7,0)
     upReg(15) := param.serial(15,8)
     upReg(16) := param.serial(23,16)
@@ -287,23 +283,7 @@ with BackBoardSlvOut16{
     upReg(7) := valueReg(15,8)
   }
 
-  // out := outPin
-
-  val isDownCDR = RegInit(false.B)
-  val isUpCDR   = RegInit(false.B)
-
-  when( isCrcPass ){
-    isDownCDR := false.B
-    isUpCDR   := false.B
-  } .elsewhen( io.lvdsSlv.downstream_rx_cdr_err ){
-    isDownCDR := true.B
-  } .elsewhen(io. lvdsSlv.upstream_rx_cdr_err ){
-    isUpCDR   := true.B
-  }
-
-  //override
-  out := Mux( isDownCDR & isUpCDR, "h5555".U, Mux(isDownCDR, Cat(Fill(16, flash1HZ)), Mux( isUpCDR, Cat(Fill(16, flash2HZ)), outPin )))
-
+  out := outPin
 
 }