From d3a17e50c280bfddfe8719b28d040fbcafc978f0 Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Wed, 3 Apr 2024 10:40:29 +0800
Subject: [PATCH] =?UTF-8?q?=E5=8E=9F=E5=8A=9F=E8=83=BD=E4=BF=9D=E6=8C=81?=
 =?UTF-8?q?=E4=B8=8D=E5=8F=98=EF=BC=8C=E5=A2=9E=E5=8A=A0=E5=8D=95=E6=92=AD?=
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---
 src/main/scala/backBoard/BackBoardMst.scala | 141 ++++++++++++++++----
 1 file changed, 118 insertions(+), 23 deletions(-)

diff --git a/src/main/scala/backBoard/BackBoardMst.scala b/src/main/scala/backBoard/BackBoardMst.scala
index f62c652..dd7edc1 100644
--- a/src/main/scala/backBoard/BackBoardMst.scala
+++ b/src/main/scala/backBoard/BackBoardMst.scala
@@ -53,6 +53,7 @@ class BackBoardMstBase extends Module{ //10M
   assert( ~(mirrorReg.io.enwB & mirrorReg.io.enrB) )
 
   val ctrlTransmit = RegInit( false.B )
+  val ctrlUnicast  = RegInit( false.B )
   val ctrlSynch    = RegInit( false.B )
   val ctrlInit     = RegInit( false.B )
 
@@ -141,6 +142,10 @@ trait BackBoardMstFSMC{ this: BackBoardMstBase =>
     when( mirrorReg.io.datarB === 5.U ){
       ctrlTransmit := true.B      
     }
+
+    when( mirrorReg.io.datarB === 6.U ){
+      ctrlUnicast := true.B      
+    }
   }
 
 }
@@ -422,32 +427,95 @@ trait BackBoardMstLVDSTransmit{ this: BackBoardMstLVDSBase =>
   }
 
 
-  val addrr = RegInit(0.U(11.W))
-  val addrw = RegInit(0.U(11.W))
 
-  when( isTransStart ){
-    addrw := 0.U
-  } .elsewhen( lvdsMst.io.rx_data_valid & ctrlTransmit){
-    assert( (stateCur === 5.U) || (stateCur === 6.U) )
-    addrw := addrw + 1.U
-  }
-
-  when( isTransStart ){
-    addrr := 0.U
-  } .elsewhen( lvdsMst.io.tx_data_ready & ctrlTransmit){
-    addrr := addrr + 1.U
-  }
-
-  mirrorDown.io.enr := (stateCur === 4.U || stateCur === 5.U) & ctrlTransmit
-  lvdsMst.io.tx_data_in := mirrorDown.io.datar
-  mirrorDown.io.addrr := addrr
-  
-  mirrorUp.io.enw    := lvdsMst.io.rx_data_valid & ctrlTransmit
-  mirrorUp.io.dataw := lvdsMst.io.rx_data_out
-  mirrorUp.io.addrw := addrw
 
 }
 
+trait BackBoardMstLVDSUnicast{ this: BackBoardMstLVDSBase =>
+
+  val isUnicast = ctrlUnicast & ~RegNext(ctrlUnicast, false.B)
+
+  when(ctrlUnicast){
+    when( isUnicast ){  //reset
+      stateCur := 0.U
+
+      frame_info_update_en := false.B
+      slave_type_num       := 0.U
+
+      tx_start := false.B
+      
+
+    }  .elsewhen( stateCur === 0.U ){ //statusUnicast
+      stateCur := 1.U
+
+      mirrorReg.io.addrB  := 13.U
+      mirrorReg.io.datawB := 0.U
+      mirrorReg.io.enwB   := true.B
+    } .elsewhen( stateCur === 1.U ){ //slvnum
+      stateCur := 2.U
+
+      mirrorReg.io.addrB  := 2.U
+      mirrorReg.io.enrB   := true.B
+
+    } .elsewhen( stateCur === 2.U ){ //slaveDataLength
+      stateCur := 3.U
+
+      //lock slvNum
+      slvNum := mirrorReg.io.datarB
+
+      mirrorReg.io.addrB  := 6.U
+      mirrorReg.io.enrB   := true.B
+
+    } .elsewhen( stateCur === 3.U  ){ //setting
+      stateCur := 4.U
+
+      //lock slaveDataLength
+      slaveDataLength := mirrorReg.io.datarB
+
+      frame_info_update_en := true.B
+      slave_type_num       := Cat( "b11".U(2.W), slvNum )
+      // slaveDataLength      := slaveDataLength
+
+      tx_start := false.B
+    } .elsewhen( stateCur === 4.U ){ // tx start
+      stateCur := 5.U
+
+      frame_info_update_en := false.B
+      tx_start := true.B
+
+    } .elsewhen( stateCur === 5.U ){ //waiting  for busy drop
+
+      tx_start := false.B
+
+      when( RegNext(lvdsMst.io.downstream_busy, false.B) & ~lvdsMst.io.downstream_busy ){
+        stateCur := 6.U
+      }
+
+    } .elsewhen( stateCur === 6.U ){
+      when( lvdsMst.io.upstream_crc_valid ){
+        stateCur := 7.U
+
+        //statusUnicast
+        mirrorReg.io.addrB  := 13.U
+        mirrorReg.io.datawB := 1.U
+        mirrorReg.io.enwB   := true.B
+
+        ctrlUnicast := false.B
+        interrupt    := true.B
+      }
+
+    } .elsewhen( stateCur === 7.U ){  
+      // stateCur := 8.U
+
+    } .otherwise{
+
+    }
+  }
+
+}
+
+
+
 trait BackBoardMstLVDSError{ this: BackBoardMstLVDSBase =>
   when( lvdsMst.io.closed_loop_err ){
 
@@ -488,4 +556,31 @@ class BackBoardMst extends BackBoardMstLVDSBase
 with BackBoardMstLVDSInit
 with BackBoardMstLVDSSync
 with BackBoardMstLVDSTransmit
-with BackBoardMstLVDSError
+with BackBoardMstLVDSUnicast
+with BackBoardMstLVDSError{
+
+  val addrr = RegInit(0.U(11.W))
+  val addrw = RegInit(0.U(11.W))
+
+  when( isTransStart | isUnicast ){
+    addrw := 0.U
+  } .elsewhen( lvdsMst.io.rx_data_valid & (ctrlTransmit | ctrlUnicast) ){
+    assert( (stateCur === 5.U) || (stateCur === 6.U) )
+    addrw := addrw + 1.U
+  }
+
+  when( isTransStart | isUnicast ){
+    addrr := 0.U
+  } .elsewhen( lvdsMst.io.tx_data_ready & (ctrlTransmit | ctrlUnicast) ){
+    addrr := addrr + 1.U
+  }
+
+  mirrorDown.io.enr := (stateCur === 4.U || stateCur === 5.U) & (ctrlTransmit | ctrlUnicast)
+  lvdsMst.io.tx_data_in := mirrorDown.io.datar
+  mirrorDown.io.addrr := addrr
+  
+  mirrorUp.io.enw    := lvdsMst.io.rx_data_valid & (ctrlTransmit | ctrlUnicast)
+  mirrorUp.io.dataw := lvdsMst.io.rx_data_out
+  mirrorUp.io.addrw := addrw
+  
+}