From d3177164a976d8c6ed867a1969af3c567c846163 Mon Sep 17 00:00:00 2001
From: RuigeLee <wut.ruigeli@gmail.com>
Date: Mon, 2 Feb 2026 17:44:25 +0800
Subject: [PATCH] =?UTF-8?q?bug=E4=BF=AE=E5=A4=8D=EF=BC=8C=E5=BC=82?=
 =?UTF-8?q?=E6=AD=A5aqspi=E7=9A=84=E8=AF=BB=E6=93=8D=E4=BD=9C=E7=9B=B8?=
 =?UTF-8?q?=E5=85=B3byteSel=E4=BB=A5=E5=8F=8A=E8=A1=A5=E5=85=85=E8=AF=BB?=
 =?UTF-8?q?=E5=8F=96=E7=BB=93=E6=9E=9Cpingpong=E9=80=89=E6=8B=A9=E5=AF=84?=
 =?UTF-8?q?=E5=AD=98=E5=99=A8isAsyncRead?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 src/main/scala/backBoard/shin/NSpiInterface.scala | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/backBoard/shin/NSpiInterface.scala b/src/main/scala/backBoard/shin/NSpiInterface.scala
index 110c6a4..c726a24 100644
--- a/src/main/scala/backBoard/shin/NSpiInterface.scala
+++ b/src/main/scala/backBoard/shin/NSpiInterface.scala
@@ -73,14 +73,18 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
     }    
   }
 
-
+  val isAsyncRead = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(false.B)}
 
   when( bitSel.andR ){ //4线操作
-    when( isSpiRead ){
-      when( isPing_async ){ //取巧//应该增强约束
+    when((byteSel === 0.U || byteSel === 1.U || byteSel === 2.U ) ){
+      exRego := 0.U //地址0, 地址1，cmd
+    } .elsewhen( isSpiRead ){
+      when( ~isAsyncRead ){ //取巧//应该增强约束
         exRego := datar_sync(0)
+        isAsyncRead := ~isAsyncRead
       } .otherwise{
         exRego := datar_sync(1)
+        isAsyncRead := ~isAsyncRead
       }
     }
   } .otherwise{ //4线操作
@@ -160,7 +164,7 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
     } .otherwise{
       isEnR_async(1) := true.B
     }
-  } .elsewhen( bitSel.andR ){
+  } .elsewhen( bitSel =/= 0.U ){
     isEnR_async(0) := false.B
     isEnR_async(1) := false.B
   }