diff --git a/src/main/scala/backBoard/shin/NSpiInterface.scala b/src/main/scala/backBoard/shin/NSpiInterface.scala
index 110c6a4..c726a24 100644
--- a/src/main/scala/backBoard/shin/NSpiInterface.scala
+++ b/src/main/scala/backBoard/shin/NSpiInterface.scala
@@ -73,14 +73,18 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
     }    
   }
 
-
+  val isAsyncRead = withClockAndReset(negedge_sck, qspi.csn.asAsyncReset){RegInit(false.B)}
 
   when( bitSel.andR ){ //4线操作
-    when( isSpiRead ){
-      when( isPing_async ){ //取巧//应该增强约束
+    when((byteSel === 0.U || byteSel === 1.U || byteSel === 2.U ) ){
+      exRego := 0.U //地址0, 地址1，cmd
+    } .elsewhen( isSpiRead ){
+      when( ~isAsyncRead ){ //取巧//应该增强约束
         exRego := datar_sync(0)
+        isAsyncRead := ~isAsyncRead
       } .otherwise{
         exRego := datar_sync(1)
+        isAsyncRead := ~isAsyncRead
       }
     }
   } .otherwise{ //4线操作
@@ -160,7 +164,7 @@ trait SyncSpiAsync{ this: SyncSpiInterfaceBase =>
     } .otherwise{
       isEnR_async(1) := true.B
     }
-  } .elsewhen( bitSel.andR ){
+  } .elsewhen( bitSel =/= 0.U ){
     isEnR_async(0) := false.B
     isEnR_async(1) := false.B
   }