From d2e0f567e01a213f537d7ba99d95daeb905aacaf Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Wed, 1 Nov 2023 16:22:46 +0800 Subject: [PATCH] =?UTF-8?q?=E8=B0=83=E6=95=B4=E7=BC=93=E5=86=B2=E5=8C=BA?= =?UTF-8?q?=E7=AD=96=E7=95=A5=EF=BC=8C=E9=80=82=E5=BA=94=E9=AB=98=E5=BC=BA?= =?UTF-8?q?=E5=BA=A6=E8=B0=83=E5=BA=A6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/Switch/DMA.scala | 4 +-- src/main/scala/Switch/RxBuff.scala | 48 ++++++++++++++++++++++-------- src/main/scala/Switch/TxBuff.scala | 26 +++++++++++++--- 3 files changed, 60 insertions(+), 18 deletions(-) diff --git a/src/main/scala/Switch/DMA.scala b/src/main/scala/Switch/DMA.scala index 0b261f0..2156c6c 100644 --- a/src/main/scala/Switch/DMA.scala +++ b/src/main/scala/Switch/DMA.scala @@ -31,8 +31,8 @@ abstract class DMAMstBase(val edgeOut: TLEdgeOut)(implicit p: Parameters) extend val io: SwitchMuxIO = IO(new SwitchMuxIO) val (_, _, isLastD, transDCnt) = edgeOut.count(io.dmaMst.D) - val rxBuff = Module(new RxBuff) - val txBuff = Module(new TxBuff) + val rxBuff = Module(new RxBuff(8)) + val txBuff = Module(new TxBuff(0)) rxBuff.io.header.ready := true.B diff --git a/src/main/scala/Switch/RxBuff.scala b/src/main/scala/Switch/RxBuff.scala index 02e8bd8..c997485 100644 --- a/src/main/scala/Switch/RxBuff.scala +++ b/src/main/scala/Switch/RxBuff.scala @@ -17,7 +17,7 @@ class RxBuffIO extends Bundle{ -class RxBuffBase extends Module{ +class RxBuffBase(val threshold: Int = 32) extends Module{ val io: RxBuffIO = IO(new RxBuffIO) val isEnqPi = RegInit(true.B) @@ -32,8 +32,10 @@ class RxBuffBase extends Module{ val header = for( i <- 0 until 2 ) yield { Reg(Vec( 20, UInt(8.W) )) } val hValid = for( i <- 0 until 2 ) yield { RegInit(false.B) } + val isReach = for( i <- 0 until 2 ) yield { RegInit(false.B) } + + val recCnt = RegInit(0.U(12.W)) - val recCnt = RegInit(0.U(5.W)) } @@ -60,20 +62,36 @@ trait RxBuffEnq{ this: RxBuffBase => when( io.enq.fire ){ when( io.enq.bits.isStart ){ recCnt := 0.U - } .elsewhen( recCnt < 20.U ){ + } .otherwise{ recCnt := recCnt + 1.U - when( isEnqPi ){ - header(0)(recCnt) := io.enq.bits.data - } .elsewhen( isEnqPo ){ - header(1)(recCnt) := io.enq.bits.data + } + } + + when( io.enq.fire ){ + when( recCnt < 20.U ){ + when( isEnqPi ){ header(0)(recCnt) := io.enq.bits.data } + .elsewhen( isEnqPo ){ header(1)(recCnt) := io.enq.bits.data } .otherwise{ assert(false.B, "Assert Failed, Rx Under Run") } - } .elsewhen( recCnt === 20.U ){ - recCnt := 21.U } } + when( io.enq.fire ){ + when( io.enq.bits.isStart ){ + when( isEnqPi ){ isReach(0) := false.B } + when( isEnqPo ){ isReach(1) := false.B } + } .elsewhen( + io.enq.bits.isLast || + (if( threshold != 0 ) {recCnt === threshold.U } else {false.B}) + ){ + when( isEnqPi ){ isReach(0) := true.B } + when( isEnqPo ){ isReach(1) := true.B } + } + } + + + } trait RxBuffDeq{ this: RxBuffBase => @@ -93,14 +111,20 @@ trait RxBuffDeq{ this: RxBuffBase => when( isDeqPi ){ - io.deq <> buff(0).io.deq + io.deq.valid := buff(0).io.deq.valid & isReach(0) + io.deq.bits := buff(0).io.deq.bits + buff(0).io.deq.ready := io.deq.ready & isReach(0) + buff(1).io.deq.ready := false.B io.header.valid := hValid(0) io.header.bits := header(0) } .otherwise{ assert( isDeqPo ) - io.deq <> buff(1).io.deq + io.deq.valid := buff(1).io.deq.valid & isReach(1) + io.deq.bits := buff(1).io.deq.bits + buff(1).io.deq.ready := io.deq.ready & isReach(1) + buff(0).io.deq.ready := false.B io.header.valid := hValid(1) @@ -112,7 +136,7 @@ trait RxBuffDeq{ this: RxBuffBase => } -class RxBuff extends RxBuffBase with RxBuffEnq with RxBuffDeq{ +class RxBuff(threshold: Int = 8) extends RxBuffBase(threshold) with RxBuffEnq with RxBuffDeq{ } diff --git a/src/main/scala/Switch/TxBuff.scala b/src/main/scala/Switch/TxBuff.scala index 9c45784..d4e1830 100644 --- a/src/main/scala/Switch/TxBuff.scala +++ b/src/main/scala/Switch/TxBuff.scala @@ -14,7 +14,7 @@ class TxBuffIO extends Bundle{ } -abstract class TxBuffBase extends Module{ +abstract class TxBuffBase(val threshold: Int = 8) extends Module{ val io: TxBuffIO = IO(new TxBuffIO) val buff = Module(new Queue( new Mac_Stream_Bundle, 2048 )) @@ -32,6 +32,8 @@ trait TxBuffEnq{ this: TxBuffBase => enqCnt := 0.U } .elsewhen( io.enq.bits.isLast ){ + } .elsewhen( enqCnt === threshold.U ){ + enqCnt := enqCnt } .otherwise{ enqCnt := enqCnt + 1.U } @@ -41,10 +43,26 @@ trait TxBuffEnq{ this: TxBuffBase => trait TxBuffDeq{ this: TxBuffBase => + val isReach = RegInit(false.B) + + when( io.enq.fire ){ + when( io.enq.bits.isStart ) { + isReach := false.B + } .elsewhen( + io.enq.bits.isLast || + (if( threshold != 0 ) {enqCnt === threshold.U} else {false.B}) + ){ + isReach := true.B + } + } + + + enqCnt === threshold.U + io.deq.bits := buff.io.deq.bits - io.deq.valid := buff.io.deq.valid - buff.io.deq.ready := io.deq.ready + io.deq.valid := buff.io.deq.valid & isReach + buff.io.deq.ready := io.deq.ready & isReach } -class TxBuff extends TxBuffBase with TxBuffEnq with TxBuffDeq +class TxBuff(threshold: Int = 8) extends TxBuffBase(threshold) with TxBuffEnq with TxBuffDeq