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devide gowin file

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This commit is contained in:
RuigeLee
2023-08-21 11:46:50 +08:00
parent 20ddabbfb3
commit d162b8f75c
2 changed files with 89 additions and 82 deletions
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89
src/main/scala/backBoard/goWinBusMst.scala Normal file
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@@ -0,0 +1,89 @@
package BACK
import chisel3._
import chisel3.util._
class Lvds_Bus_MasterIO extends Bundle{
val rst_n = Input(Bool())
val oser_pclk = Input(Bool())
val oser_fclk = Input(Bool())
val ides_pclk = Input(Bool())
val ides_fclk = Input(Bool())
val lvds_down_dout = Output(Bool())
val lvds_up_din = Input(Bool())
val frame_info_update_en = Input(Bool())
val slave_type_num = Input(UInt(8.W))
val slave_data_length = Input(UInt(8.W))
val tx_start = Input(Bool())
val tx_data_in = Input(UInt(8.W))
val tx_data_ready = Output(Bool())
val downstream_busy = Output(Bool())
val rx_data_out = Output(UInt(8.W))
val rx_data_valid = Output(Bool())
val upstream_crc_valid = Output(Bool())
val upstream_crc_err = Output(Bool())
val upstream_crc_err_count = Output(UInt(8.W))
val upstream_cdr_err = Output(Bool())
}
class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline {
val io: Lvds_Bus_MasterIO = IO(new Lvds_Bus_MasterIO)
setInline("lvds_bus_master.v",
"""
| module Lvds_Bus_Master(
| input rst_n,
| input oser_pclk,
| input oser_fclk,
| input ides_pclk,
| input ides_fclk,
| output lvds_down_dout,
| input lvds_up_din,
| input frame_info_update_en,
| input [7:0] slave_type_num,
| input [7:0]slave_data_length,
| input tx_start,
| input [7:0] tx_data_in,
| output tx_data_ready,
| output downstream_busy,
| output [7:0] rx_data_out,
| output rx_data_valid,
| output upstream_crc_valid,
| output upstream_crc_err,
| output [7:0] upstream_crc_err_count,
| output upstream_cdr_err
| );
| lvds_bus_master_top i_lvds_bus_master(
| .rst_n(rst_n), //input
| .oser_pclk(oser_pclk), //input
| .oser_fclk(oser_fclk), //input
| .ides_pclk(ides_pclk), //input
| .ides_fclk(ides_fclk), //input
|
| .lvds_down_dout(lvds_down_dout), //output
| .lvds_up_din(lvds_up_din), //input
|
| .frame_info_update_en(frame_info_update_en), //input
| .slave_type_num(slave_type_num), //input [7:0]
| .slave_data_length(slave_data_length), //input [7:0]
| .tx_start(tx_start), //input
| .tx_data_in(tx_data_in), //input [7:0]
| .tx_data_ready(tx_data_ready), //output
| .downstream_busy(downstream_busy), //output
| .rx_data_out(rx_data_out), //output [7:0]
| .rx_data_valid(rx_data_valid), //output
| .upstream_crc_valid(upstream_crc_valid), //output
| .upstream_crc_err(upstream_crc_err), //output
| .upstream_crc_err_count(upstream_crc_err_count), //output [7:0]
| .upstream_cdr_err(upstream_cdr_err) //output
| );
|endmodule
""".stripMargin)
}

82
src/main/scala/backBoard/goWinBus.scala → src/main/scala/backBoard/goWinBusSlv.scala
View File

@@ -11,88 +11,6 @@ class CRC_ERR_Bundle extends Bundle{
val cdr_err = Bool() val cdr_err = Bool()
} }
class Lvds_Bus_MasterIO extends Bundle{
val rst_n = Input(Bool())
val oser_pclk = Input(Bool())
val oser_fclk = Input(Bool())
val ides_pclk = Input(Bool())
val ides_fclk = Input(Bool())
val lvds_down_dout = Output(Bool())
val lvds_up_din = Input(Bool())
val frame_info_update_en = Input(Bool())
val slave_type_num = Input(UInt(8.W))
val slave_data_length = Input(UInt(8.W))
val tx_start = Input(Bool())
val tx_data_in = Input(UInt(8.W))
val tx_data_ready = Output(Bool())
val downstream_busy = Output(Bool())
val rx_data_out = Output(UInt(8.W))
val rx_data_valid = Output(Bool())
val upstream_crc_valid = Output(Bool())
val upstream_crc_err = Output(Bool())
val upstream_crc_err_count = Output(UInt(8.W))
val upstream_cdr_err = Output(Bool())
}
class Lvds_Bus_Master extends BlackBox with HasBlackBoxInline {
val io: Lvds_Bus_MasterIO = IO(new Lvds_Bus_MasterIO)
setInline("lvds_bus_master.v",
"""
| module Lvds_Bus_Master(
| input rst_n,
| input oser_pclk,
| input oser_fclk,
| input ides_pclk,
| input ides_fclk,
| output lvds_down_dout,
| input lvds_up_din,
| input frame_info_update_en,
| input [7:0] slave_type_num,
| input [7:0]slave_data_length,
| input tx_start,
| input [7:0] tx_data_in,
| output tx_data_ready,
| output downstream_busy,
| output [7:0] rx_data_out,
| output rx_data_valid,
| output upstream_crc_valid,
| output upstream_crc_err,
| output [7:0] upstream_crc_err_count,
| output upstream_cdr_err
| );
| lvds_bus_master_top i_lvds_bus_master(
| .rst_n(rst_n), //input
| .oser_pclk(oser_pclk), //input
| .oser_fclk(oser_fclk), //input
| .ides_pclk(ides_pclk), //input
| .ides_fclk(ides_fclk), //input
|
| .lvds_down_dout(lvds_down_dout), //output
| .lvds_up_din(lvds_up_din), //input
|
| .frame_info_update_en(frame_info_update_en), //input
| .slave_type_num(slave_type_num), //input [7:0]
| .slave_data_length(slave_data_length), //input [7:0]
| .tx_start(tx_start), //input
| .tx_data_in(tx_data_in), //input [7:0]
| .tx_data_ready(tx_data_ready), //output
| .downstream_busy(downstream_busy), //output
| .rx_data_out(rx_data_out), //output [7:0]
| .rx_data_valid(rx_data_valid), //output
| .upstream_crc_valid(upstream_crc_valid), //output
| .upstream_crc_err(upstream_crc_err), //output
| .upstream_crc_err_count(upstream_crc_err_count), //output [7:0]
| .upstream_cdr_err(upstream_cdr_err) //output
| );
|endmodule
""".stripMargin)
}
class Lvds_Bus_SlaveIO extends Bundle{ class Lvds_Bus_SlaveIO extends Bundle{
val rst_n = Input(Bool()) val rst_n = Input(Bool())