From d0a0fe28362ed11298b99f503c8d1da745238c1c Mon Sep 17 00:00:00 2001 From: RuigeLee Date: Wed, 28 Jan 2026 16:37:43 +0800 Subject: [PATCH] =?UTF-8?q?=E8=B0=83=E6=95=B4=E5=90=8C=E6=AD=A5spi?= =?UTF-8?q?=E7=9A=84enw=20enr=E7=9A=84byte=E6=95=B0?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/shin/SpiInterface.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/backBoard/shin/SpiInterface.scala b/src/main/scala/backBoard/shin/SpiInterface.scala index 33a8593..208cdbc 100644 --- a/src/main/scala/backBoard/shin/SpiInterface.scala +++ b/src/main/scala/backBoard/shin/SpiInterface.scala @@ -65,8 +65,8 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{ val spiLenTemp = RegInit(2.U(12.W)) val spiCnt = RegInit(0.U(12.W)) - io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(2) & bitSelNext.andR & isSpiWrite & byteSelNext >= 3.U & (spiCnt < spiLen) - io.isEnR := (isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 3.U ) & (spiCnt <= spiLen) + io.isEnW := isSckPosedgeNext(0) & ~shiftCSn(2) & bitSelNext.andR & isSpiWrite & byteSelNext >= 4.U & (spiCnt < spiLen) + io.isEnR := (isSckPosedge & ~shiftCSn(1) & bitSel === 0.U & isSpiRead & byteSel >= 4.U ) & (spiCnt <= spiLen) io.dataw := exRegi io.addrr := addrr @@ -104,7 +104,7 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{ } .elsewhen(isSckPosedge & ~shiftCSn(1) & bitSel.andR & byteSel === 1.U) {//CS为低，且SCK上跳的第0byte addrr := Cat(addrr(7,0), exRegi(6,0), shiftMOSI) } .otherwise{ // byteSel > 1.U - when( isSckPosedge & byteSel >= 3.U & bitSel === 0.U ){ + when( isSckPosedge & byteSel >= 4.U & bitSel === 0.U ){ addrr := addrr + 1.U } }