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测试：删除PR灯节省资源，删除滤波器，粘滞现象结束

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This commit is contained in:
RuigeLee
2024-04-14 18:05:38 +08:00
parent 1721d332ad
commit d0806a0433
1 changed files with 79 additions and 78 deletions
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157
src/main/scala/backBoard/LocalRegisters.scala
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@@ -112,12 +112,14 @@ trait BackBoardSlvStatusPR { this: BackBoardSlvLocal =>
val LED_PR = IO(Output( Bool() )) val LED_PR = IO(Output( Bool() ))
LED_PR := ~Mux1H(Seq( LED_PR := false.B
( statusPR === "b00".U ) -> flash2HZ,
( statusPR === "b01".U ) -> flash1HZ, // ~Mux1H(Seq(
( statusPR === "b10".U ) -> true.B, // ( statusPR === "b00".U ) -> flash2HZ,
( statusPR === "b11".U ) -> false.B, // ( statusPR === "b01".U ) -> flash1HZ,
)) // ( statusPR === "b10".U ) -> true.B,
// ( statusPR === "b11".U ) -> false.B,
// ))
} }
@@ -131,104 +133,103 @@ trait BackBoardSlvIn { this: BackBoardSlvLocal =>
val in = IO(Input(UInt((8*gp).W))) val in = IO(Input(UInt((8*gp).W)))
val flitCnt = RegInit(MixedVecInit(Seq( 0.U(1.W), 0.U((log2Ceil(256/flitNum)).W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W)) )) // val flitCnt = RegInit(MixedVecInit(Seq( 0.U(1.W), 0.U((log2Ceil(256/flitNum)).W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W), 0.U(1.W)) ))
val flitTrigger = Wire(Vec(9, Bool())) // val flitTrigger = Wire(Vec(9, Bool()))
flitTrigger(0) := ~RegNext(flitTrigger(0)) // flitTrigger(0) := ~RegNext(flitTrigger(0))
// flitTrigger(1) := usTrigger // flitTrigger(1) := flitCnt(1) >= (256/flitNum-1).U
// when( ~RegNext(usTrigger) & usTrigger ){
// when( flitTrigger(1) ){
// flitCnt(1) := 0.U
// } .otherwise{
// flitCnt(1) := flitCnt(1) + 1.U
// }
flitTrigger(1) := flitCnt(1) >= (256/flitNum-1).U // }
when( ~RegNext(usTrigger) & usTrigger ){
when( flitTrigger(1) ){
flitCnt(1) := 0.U
} .otherwise{
flitCnt(1) := flitCnt(1) + 1.U
}
} // flitTrigger(2) := flitCnt(2) === 1.U
// when( ~RegNext(flitTrigger(1)) & flitTrigger(1) ){
// flitCnt(2) := flitCnt(2) + 1.U
// }
flitTrigger(2) := flitCnt(2) === 1.U // flitTrigger(3) := flitCnt(3) === 1.U
when( ~RegNext(flitTrigger(1)) & flitTrigger(1) ){ // when( ~RegNext(flitTrigger(2)) & flitTrigger(2) ){
flitCnt(2) := flitCnt(2) + 1.U // flitCnt(3) := flitCnt(3) + 1.U
} // }
flitTrigger(3) := flitCnt(3) === 1.U // flitTrigger(4) := flitCnt(4) === 1.U
when( ~RegNext(flitTrigger(2)) & flitTrigger(2) ){ // when( ~RegNext(flitTrigger(3)) & flitTrigger(3) ){
flitCnt(3) := flitCnt(3) + 1.U // flitCnt(4) := flitCnt(4) + 1.U
} // }
flitTrigger(4) := flitCnt(4) === 1.U // flitTrigger(5) := flitCnt(5) === 1.U
when( ~RegNext(flitTrigger(3)) & flitTrigger(3) ){ // when( ~RegNext(flitTrigger(4)) & flitTrigger(4) ){
flitCnt(4) := flitCnt(4) + 1.U // flitCnt(5) := flitCnt(5) + 1.U
} // }
flitTrigger(5) := flitCnt(5) === 1.U // flitTrigger(6) := flitCnt(6) === 1.U
when( ~RegNext(flitTrigger(4)) & flitTrigger(4) ){ // when( ~RegNext(flitTrigger(5)) & flitTrigger(5) ){
flitCnt(5) := flitCnt(5) + 1.U // flitCnt(6) := flitCnt(6) + 1.U
} // }
flitTrigger(6) := flitCnt(6) === 1.U // flitTrigger(7) := flitCnt(7) === 1.U
when( ~RegNext(flitTrigger(5)) & flitTrigger(5) ){ // when( ~RegNext(flitTrigger(6)) & flitTrigger(6) ){
flitCnt(6) := flitCnt(6) + 1.U // flitCnt(7) := flitCnt(7) + 1.U
} // }
flitTrigger(7) := flitCnt(7) === 1.U // flitTrigger(8) := flitCnt(8) === 1.U
when( ~RegNext(flitTrigger(6)) & flitTrigger(6) ){ // when( ~RegNext(flitTrigger(7)) & flitTrigger(7) ){
flitCnt(7) := flitCnt(7) + 1.U // flitCnt(8) := flitCnt(8) + 1.U
} // }
flitTrigger(8) := flitCnt(8) === 1.U
when( ~RegNext(flitTrigger(7)) & flitTrigger(7) ){
flitCnt(8) := flitCnt(8) + 1.U
}
for( j <- 0 until gp ) { for( j <- 0 until gp ) {
val digitalFilter = RegEnable( downReg(4+j), 1.U, statusPage === 0.U ) // val digitalFilter = RegEnable( downReg(4+j), 1.U, statusPage === 0.U )
val digitalIn = Reg( Vec(8, Bool()) ) // val digitalIn = Reg( Vec(8, Bool()) )
when( statusPage === 0.U ){ when( statusPage === 0.U ){
upReg(2+j) := Cat( digitalIn.reverse ) // upReg(2+j) := Cat( digitalIn.reverse )
upReg(2+j) := in(8*j+7, 8*j)
upReg(4+j) := downReg(4+j) upReg(4+j) := downReg(4+j)
} }
for( i <- 0 until 8 ) { // for( i <- 0 until 8 ) {
val flitter = RegInit(VecInit( Seq.fill(flitNum){false.B})) // val flitter = RegInit(VecInit( Seq.fill(flitNum){false.B}))
val flitHi = RegInit(0.U((log2Ceil(flitNum+1)).W)) // val flitHi = RegInit(0.U((log2Ceil(flitNum+1)).W))
( 0 until 9 ).map{ k => // ( 0 until 9 ).map{ k =>
when( digitalFilter === k.U ){ // when( digitalFilter === k.U ){
when( (if( k == 0 ){ true.B } else {~RegNext(flitTrigger(k)) & flitTrigger(k)}) ){ // when( (if( k == 0 ){ true.B } else {~RegNext(flitTrigger(k)) & flitTrigger(k)}) ){
flitter(0) := in(i+8*j) // flitter(0) := in(i+8*j)
(1 until flitNum).map{ k => // (1 until flitNum).map{ k =>
flitter(k) := flitter(k-1) // flitter(k) := flitter(k-1)
} // }
when( (~flitter(flitNum-1) & ~in(i+8*j)) | (flitter(flitNum-1) & in(i+8*j)) ){ // when( (~flitter(flitNum-1) & ~in(i+8*j)) | (flitter(flitNum-1) & in(i+8*j)) ){
flitHi := flitHi // flitHi := flitHi
} .elsewhen( ~flitter(flitNum-1) & in(i+8*j) ){ // } .elsewhen( ~flitter(flitNum-1) & in(i+8*j) ){
flitHi := flitHi + 1.U // flitHi := flitHi + 1.U
} .elsewhen( flitter(flitNum-1) & ~in(i+8*j) ){ // } .elsewhen( flitter(flitNum-1) & ~in(i+8*j) ){
flitHi := flitHi - 1.U // flitHi := flitHi - 1.U
} // }
when( flitHi >= (flitNum*4/5).U ){ // when( flitHi >= (flitNum*4/5).U ){
digitalIn(i) := true.B // digitalIn(i) := true.B
} .elsewhen( flitHi <= (flitNum/5).U ){ // } .elsewhen( flitHi <= (flitNum/5).U ){
digitalIn(i) := false.B // digitalIn(i) := false.B
} // }
assert( flitHi <= flitNum.U ) // assert( flitHi <= flitNum.U )
assert( flitter.count( (k:Bool) => k === true.B ) === flitHi ) // assert( flitter.count( (k:Bool) => k === true.B ) === flitHi )
} // }
} // }
} // }
} // }
} }
} }