断言不会发生tx Underrun

src/main/scala/mac/MAC.scala

@@ -125,7 +125,6 @@ val TxUsedData = Wire(Bool())
 val TxData     = Wire(UInt(8.W))
 val TxRetry    = Wire(Bool())
 val TxAbort    = Wire(Bool())
-val TxUnderRun = Wire(Bool())
 val TxDone     = Wire(Bool())
 val TPauseRq = Wire(Bool())
 
@@ -135,7 +134,6 @@ dontTouch(TxUsedData)
 dontTouch(TxData    )
 dontTouch(TxRetry   )
 dontTouch(TxAbort   )
-dontTouch(TxUnderRun)
 dontTouch(TxDone    )
 dontTouch(TPauseRq  )
 
@@ -512,7 +510,6 @@ val txethmac = withClockAndReset(io.mtx_clk_pad_i.asClock, io.asyncReset)( Modul
 
 txethmac.io.TxStartFrm      := TxStartFrmOut
 txethmac.io.TxEndFrm        := TxEndFrmOut
-txethmac.io.TxUnderRun      := TxUnderRun
 txethmac.io.TxData          := TxDataOut
 txethmac.io.CarrierSense    := TxCarrierSense
 txethmac.io.Collision       := Collision
@@ -817,9 +814,6 @@ val rxethmac = withClockAndReset(io.mrx_clk_pad_i.asClock, io.asyncReset)( Modul
   TxEndFrm        := macTileLinkTx.io.TxEndFrm
   TxData          := macTileLinkTx.io.TxData
 
-              wishbone.io.TxUnderRun := TxUnderRun
-              TxUnderRun      := macTileLinkTx.io.TxUnderRun
-              macTileLinkTx.io.TxUnderRun_wb := wishbone.io.TxUnderRun_wb
 
               macTileLinkTx.io.TxData_wb := wishbone.io.TxData_wb
               macTileLinkTx.io.TxValidBytesLatched := wishbone.io.TxValidBytesLatched

src/main/scala/mac/MacTileLinkTx.scala

@@ -12,7 +12,6 @@ class MacTileLinkTxIO extends Bundle{
   val TxStartFrm     = Output(Bool())     // Transmit packet start frame
   val TxEndFrm       = Output(Bool())     // Transmit packet end frame
   val TxData         = Output(UInt(8.W))  // Transmit packet data byte
-  val TxUnderRun     = Output(Bool())     // Transmit packet under-run
 
   val TxUsedData     = Input(Bool())      // Transmit packet used data
   val TxRetry        = Input(Bool())      // Transmit packet retry
@@ -25,7 +24,6 @@ class MacTileLinkTxIO extends Bundle{
   val TxEndFrm_wb = Input(Bool())
   val TxValidBytesLatched = Input(UInt(2.W))
   val TxData_wb = Input(UInt(32.W))
-  val TxUnderRun_wb = Input(Bool())
 }
 
 
@@ -40,7 +38,6 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
   val TxStartFrm = RegInit(false.B);  io.TxStartFrm := TxStartFrm
   val TxEndFrm   = RegInit(false.B);  io.TxEndFrm   := TxEndFrm
   val TxData     = RegInit(0.U(8.W)); io.TxData     := TxData
-  val TxUnderRun = RegInit(false.B);  io.TxUnderRun := TxUnderRun
   val TxDataLatched = RegInit(0.U(32.W))
   val TxByteCnt = RegInit(0.U(2.W))
   val LastWord = RegInit(false.B)
@@ -105,21 +102,6 @@ class MacTileLinkTx extends Module with RequireAsyncReset{
     TxDataLatched := io.TxData_wb
   }
 
-  val TxUnderRun_sync1 = RegInit(false.B)
-
-  // Tx under run
-  when(io.TxUnderRun_wb){
-    TxUnderRun_sync1 := true.B
-  } .elsewhen(io.BlockingTxStatusWrite_sync){
-    TxUnderRun_sync1 := false.B
-  }
-
-  // Tx under run
-  when(io.BlockingTxStatusWrite_sync){
-    TxUnderRun := false.B
-  } .elsewhen(TxUnderRun_sync1){
-    TxUnderRun := true.B
-  }
 
   // Tx Byte counter
   when(TxAbort_q | TxRetry_q){

src/main/scala/mac/MacTilelink.scala

@@ -39,8 +39,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
     val CarrierSenseLost = Input(Bool())     // Carrier Sense was lost during the frame transmission
 
     // Tx
-    val TxUsedData     = Input(Bool())      // Transmit packet used data
-    val TxUnderRun     = Input(Bool())     // Transmit packet under-run
     val PerPacketCrcEn = Output(Bool())     // Per packet crc enable
     val PerPacketPad   = Output(Bool())     // Per packet pading
 
@@ -53,16 +51,12 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
 
     val BlockingTxStatusWrite = Output(Bool())
 
-    val ReadTxDataFromFifo_sync = Input(Bool())
+    val TxUsedData     = Input(Bool())      // Transmit packet used data    
-    val TxData_wb = Output(UInt(32.W))
+   
 
     val TxValidBytesLatched = Output(UInt(2.W))
     
-    val TxStartFrm_wb = Output(Bool())
-    val TxStartFrm_syncb = Input(Bool())
-    val TxEndFrm_wb = Output(Bool())
 
-    val TxUnderRun_wb = Output(Bool())
 
     val TxRetrySync  = Input(Bool())
     val TxAbortSync = Input(Bool())      // Transmit packet abort
@@ -84,6 +78,12 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
 
 
 
+    val TxStartFrm_wb = Output(Bool())
+    val TxStartFrm_syncb = Input(Bool())
+    val TxEndFrm_wb = Output(Bool())
+
+    val TxData_wb = Output(UInt(32.W))
+    val ReadTxDataFromFifo_sync = Input(Bool())
 
     val txEnq = Flipped(new TxBuff_Deq_Bundle)
 
@@ -160,6 +160,35 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
   }
 
 
+  when((TxLength === 0.U) & io.TxUsedData){
+    TxEndFrm_wb := true.B
+  } .elsewhen(TxRetryPulse | TxDonePulse | TxAbortPulse){
+    TxEndFrm_wb := false.B
+  }
+
+  when( io.txEnq.ctrl.fire ){
+    TxStatus := Cat(txBuffDesc.irq, txBuffDesc.wr, txBuffDesc.pad, txBuffDesc.crc) // Latching status from the tx buffer descriptor Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
+    TxLength        := io.txEnq.ctrl.bits.txLength                                             //Latching length from the buffer descriptor;
+    LatchedTxLength := io.txEnq.ctrl.bits.txLength
+  } .elsewhen( io.txEnq.data.fire ){
+    when( TxLength < 4.U ){
+      TxLength := 0.U
+    } .otherwise{
+      TxLength := TxLength - 4.U    // Length is subtracted at the data request
+    }
+  }
+
+  tx_fifo.io.data_in := io.tlMst.D.bits.data
+  tx_fifo.io.write   := io.tlMst.D.fire & io.tlMst.D.bits.opcode === 1.U
+
+
+  io.txEnq.data.ready    := ReadTxDataFromFifoSyncPluse & ~tx_fifo.io.empty
+  assert( ~(io.txEnq.data.ready & ~io.txEnq.data.valid), "Assert Failed, Tx should never under run!" )
+
+  io.TxData_wb       := io.txEnq.data.bits
+
+  tx_fifo.io.clear   := TxAbortPacket | TxRetryPacket
+
 
 
 
@@ -187,7 +216,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
   val tx_fifo = Module( new MacFifo(dw = 32, dp = 16) )
   val TxB_IRQ = RegInit(false.B); io.TxB_IRQ := TxB_IRQ
   val TxE_IRQ = RegInit(false.B); io.TxE_IRQ := TxE_IRQ
-  val TxUnderRun_wb = RegInit(false.B); io.TxUnderRun_wb := TxUnderRun_wb
   val TxBDRead = RegInit(true.B)
   val TxStatusWrite = Wire(Bool())
   val TxLength = RegInit(0.U(16.W))
@@ -297,7 +325,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
         stateNxt := StateTX // wb access stage, r_RxEn is disabled but r_TxEn is enabled
 
         ram_addr := Cat(TxBDAddress, TxPointerRead) //[7,1] + [0]
-        ram_di   := Cat(LatchedTxLength, 0.U(1.W), TxStatus, 0.U(2.W), io.TxUnderRun, io.RetryCntLatched, io.RetryLimit, io.LateCollLatched, io.DeferLatched, io.CarrierSenseLost)
+        ram_di   := Cat(LatchedTxLength, 0.U(1.W), TxStatus, 0.U(2.W), false.B, io.RetryCntLatched, io.RetryLimit, io.LateCollLatched, io.DeferLatched, io.CarrierSenseLost)
       } .otherwise{
         stateNxt := StateIdle // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
       }
@@ -378,17 +406,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
 
 
   
-  when(stateNxt === StateTX & stateCur === StateTX & TxBDRead){
+
-    TxStatus := Cat(txBuffDesc.irq, txBuffDesc.wr, txBuffDesc.pad, txBuffDesc.crc) // Latching status from the tx buffer descriptor Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
-    TxLength        := txBuffDesc.len                                              //Latching length from the buffer descriptor;
-    LatchedTxLength := txBuffDesc.len 
-  } .elsewhen( MasterWbTX & io.tlMst.D.fire ){ //tx tileRead
-    when( TxLength < 4.U ){
-      TxLength := 0.U
-    } .otherwise{
-      TxLength := TxLength - 4.U    // Length is subtracted at the data request
-    }
-  }
 
 
 
@@ -427,7 +445,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
 
 
 
-  val TxError = io.TxUnderRun | io.RetryLimit | io.LateCollLatched | io.CarrierSenseLost
+  val TxError = io.RetryLimit | io.LateCollLatched | io.CarrierSenseLost
 
   // Tx Done Interrupt
   when(TxStatusWrite & TxIRQEn){
@@ -503,13 +521,6 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
 
 
 
-  tx_fifo.io.data_in := io.tlMst.D.bits.data
-  tx_fifo.io.write   := io.tlMst.D.fire & io.tlMst.D.bits.opcode === 1.U
-
-
-  tx_fifo.io.read    := ReadTxDataFromFifoSyncPluse & ~tx_fifo.io.empty
-  tx_fifo.io.clear   := TxAbortPacket | TxRetryPacket
-  io.TxData_wb       := tx_fifo.io.data_out
 
 
 
@@ -518,12 +529,8 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
 
 
 
-  // TxEndFrm_wb: indicator of the end of frame
+
-  when((TxLength === 0.U) & tx_fifo.io.almost_empty & io.TxUsedData){
+
-    TxEndFrm_wb := true.B
-  } .elsewhen(TxRetryPulse | TxDonePulse | TxAbortPulse){
-    TxEndFrm_wb := false.B
-  }
 
 
   // Marks which bytes are valid within the word.
@@ -653,12 +660,7 @@ abstract class MacTileLinkBase(edgeIn: TLEdgeIn, edgeOut: TLEdgeOut) extends Mod
   
 
 
-  // Tx under run
+
-  when(TxAbortPulse){
-    TxUnderRun_wb := false.B    
-  } .elsewhen(tx_fifo.io.empty & ReadTxDataFromFifoSyncPluse){
-    TxUnderRun_wb := true.B
-  }
 
 
 

src/main/scala/mac/MacTx.scala

@@ -8,7 +8,6 @@ class MacTxIO extends Bundle{
 
   val TxStartFrm      = Input(Bool())         // Transmit packet start frame
   val TxEndFrm        = Input(Bool())         // Transmit packet end frame
-  val TxUnderRun      = Input(Bool())         // Transmit packet under-run
   val TxData          = Input(UInt(8.W))         // Transmit packet data byte
   val CarrierSense    = Input(Bool())         // Carrier sense (synchronized)
   val Collision       = Input(Bool())         // Collision (synchronized)
@@ -65,7 +64,6 @@ abstract class MacTxBase extends Module with RequireAsyncReset{
 
   val StateSFD              = Wire(Bool())
 
-  val UnderRun              = Wire(Bool())
   val TooBig                = Wire(Bool())
 
   val CrcError              = Wire(Bool())
@@ -114,7 +112,7 @@ trait MacTxFSM { this: MacTxBase =>
   StartPreamble := StateIdle & io.TxStartFrm & ~io.CarrierSense
 
   StartData(0) := ~io.Collision & (StatePreamble & NibCntEq15 | StateData(1) & ~io.TxEndFrm)
-  StartData(1) := ~io.Collision & StateData(0) & ~io.TxUnderRun & ~MaxFrame
+  StartData(1) := ~io.Collision & StateData(0) & ~MaxFrame
 
   val StartPAD = ~io.Collision & StateData(1) & io.TxEndFrm & io.Pad & ~NibbleMinFl
 
@@ -122,7 +120,7 @@ trait MacTxFSM { this: MacTxBase =>
     (~io.Collision & StateData(1) & io.TxEndFrm & (~io.Pad | io.Pad & NibbleMinFl) & io.CrcEn) |
     (~io.Collision & StatePAD & NibbleMinFl & io.CrcEn)
 
-  StartJam := (io.Collision | UnderRun) & ((StatePreamble & NibCntEq15) | (StateData(1) | StateData(0)) | StatePAD | StateFCS)
+  StartJam := (io.Collision ) & ((StatePreamble & NibCntEq15) | (StateData(1) | StateData(0)) | StatePAD | StateFCS)
 
   StartBackoff := StateJam & ~RandomEq0 & ColWindow & ~RetryMax & NibCntEq7 & ~io.NoBckof
 
@@ -130,7 +128,7 @@ trait MacTxFSM { this: MacTxBase =>
     (StateIPG & ~Rule1 & io.CarrierSense & NibCnt(6,0) <= io.IPGR1 & NibCnt(6,0) =/= io.IPGR2) |
     (StateIdle & io.CarrierSense) |
     (StateJam & NibCntEq7 & (io.NoBckof | RandomEq0 | ~ColWindow | RetryMax)) |
-    (StateBackOff & (io.TxUnderRun | RandomEqByteCnt)) |
+    (StateBackOff & (RandomEqByteCnt)) |
     io.StartTxDone |
     TooBig
 
@@ -352,7 +350,7 @@ class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC with
   val TxAbort = RegInit(false.B); io.TxAbort := TxAbort
 
   val MTxEn = RegNext(StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS | StateJam, false.B); io.MTxEn := MTxEn
-  val MTxErr = RegNext( TooBig | UnderRun, false.B); io.MTxErr := MTxErr// Transmit error
+  val MTxErr = RegNext( TooBig, false.B); io.MTxErr := MTxErr// Transmit error
 
   val WillTransmit = RegNext(StartPreamble | StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS | StateJam, false.B); io.WillTransmit := WillTransmit// WillTransmit
 
@@ -361,13 +359,12 @@ class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC with
   io.ResetCollision := ~(StatePreamble | (StateData(0) | StateData(1)) | StatePAD | StateFCS)
   val ExcessiveDeferOccured = io.TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured
   io.StartTxDone := ~io.Collision & (StateFCS & NibCntEq7 | StateData(1) & io.TxEndFrm & (~io.Pad | io.Pad & NibbleMinFl) & ~io.CrcEn)
-  UnderRun := StateData(0) & io.TxUnderRun & ~io.Collision
+  TooBig := ~io.Collision & MaxFrame & (StateData(0) | StateFCS);
-  TooBig := ~io.Collision & MaxFrame & (StateData(0) & ~io.TxUnderRun | StateFCS);
+  val StartTxRetry = StartJam & (ColWindow & ~RetryMax)
-  val StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
+  io.LateCollision := StartJam & ~ColWindow
-  io.LateCollision := StartJam & ~ColWindow & ~UnderRun;
   io.MaxCollisionOccured := StartJam & ColWindow & RetryMax;
   StateSFD := StatePreamble & NibCntEq15;
-  io.StartTxAbort := TooBig | UnderRun | ExcessiveDeferOccured | io.LateCollision | io.MaxCollisionOccured
+  io.StartTxAbort := TooBig | ExcessiveDeferOccured | io.LateCollision | io.MaxCollisionOccured
 
   when(~io.TxStartFrm){
     StopExcessiveDeferOccured := false.B
@@ -417,7 +414,7 @@ class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC with
   }
 
   // Retry counter
-  when(ExcessiveDeferOccured | UnderRun | TooBig | io.StartTxDone | io.TxUnderRun 
+  when(ExcessiveDeferOccured | TooBig | io.StartTxDone
       | StateJam & NibCntEq7 & (~ColWindow | RetryMax)){
     RetryCnt := 0.U
   }.elsewhen(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | io.NoBckof) | StateBackOff & RandomEqByteCnt){
@@ -443,7 +440,7 @@ class MacTx extends MacTxBase with MacTxFSM with MacTxCounter with MacTxCRC with
       )
   }
 
-  val PacketFinished_d = io.StartTxDone | TooBig | UnderRun | io.LateCollision | io.MaxCollisionOccured | ExcessiveDeferOccured;
+  val PacketFinished_d = io.StartTxDone | TooBig | io.LateCollision | io.MaxCollisionOccured | ExcessiveDeferOccured;
   val PacketFinished = RegNext(PacketFinished_d, false.B)
   when(true.B){
     PacketFinished_q := PacketFinished