io merge

src/main/verilog/backBoardSlvTop.v

@@ -15,9 +15,8 @@ module slave_top(
   output lvds_down_dout_p,
   output lvds_down_dout_n,
 
-  input  [31:0] in,
-  output [31:0] out,
-  output [31:0] oe
+  inout [31:0] digitalIO
+
 );
 
 wire clk_400m;
@@ -29,6 +28,10 @@ wire clk_10m;
 reg        rst_n;
 reg        rstn_d;
 
+wire [31:0] in;
+wire [31:0] out;
+wire [31:0] oe;
+
 
 always@(posedge clk_10m) begin
     rstn_d <= resetn;
@@ -44,6 +47,18 @@ Gowin_PLLO Gowin_PLLO(
         .clkin(clock)
     );
 
+generate
+    for( genvar i = 0; i < 32; i = i + 1 ) begin
+        IOBUF uut(
+            .O(in[i]),
+            .IO(digitalIO[i]),
+            .I(out[i]),
+            .OEN(~oe[i])
+        );
+    end
+endgenerate
+
+
 TLVDS_OBUF lvds_downstream_out(
   .O(lvds_down_dout_p),
   .OB(lvds_down_dout_n),