diff --git a/src/main/scala/backBoard/pico/BackSystem.scala b/src/main/scala/backBoard/pico/BackSystem.scala
index 1b3ed9f..afc65b0 100644
--- a/src/main/scala/backBoard/pico/BackSystem.scala
+++ b/src/main/scala/backBoard/pico/BackSystem.scala
@@ -117,7 +117,7 @@ class BackSysImp(outer: BackSys) extends LazyModuleImp(outer) with HasBackParame
   val cdr = for( i <- 0 until 2 ) yield { Module(new TLCDR(cdr_edge)) }
 
     // val trap = Output(Bool())
-  pico.io.irq := 0.U
+  pico.io.irq := Cat( cdr(1).io.interrupt.asUInt, cdr(0).io.interrupt.asUInt )
     // val eoi = Output(UInt(32.W))
 
 
diff --git a/src/main/scala/backBoard/pico/TLCDR.scala b/src/main/scala/backBoard/pico/TLCDR.scala
index 4ac6767..cf8a2fd 100644
--- a/src/main/scala/backBoard/pico/TLCDR.scala
+++ b/src/main/scala/backBoard/pico/TLCDR.scala
@@ -17,6 +17,8 @@ abstract class TLCDRBase(val edge: TLEdgeIn)(implicit p: Parameters) extends Bac
 
     val tla = Flipped(new DecoupledIO(new TLBundleA(edge.bundle)))
     val tld = new DecoupledIO(new TLBundleD(edge.bundle))
+
+    val interrupt = Output(Vec(5, Bool()))
   }
 
   val io: TLCDRIO = IO(new TLCDRIO)  
@@ -190,6 +192,16 @@ class TLCDR(edge: TLEdgeIn)(implicit p: Parameters) extends TLCDRBase(edge) with
   io.tla.ready := tlAReady
   io.tld.valid := tlDValid
 
+  io.interrupt(0) := intTxError
+  io.interrupt(1) := intTxFifoFull
+  io.interrupt(2) := intTxFinish
+
+  io.interrupt(3) := intRxError
+  io.interrupt(4) := intRxValid
+
+
+
+
 
   when( io.tla.fire ) {
     tlaInfo := io.tla.bits