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增加测试用例,将频率差改到120ppm,测试未通过

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bacon
2025-09-01 17:00:19 +08:00
parent b8da95422e
commit cce1cf4179
1 changed files with 34 additions and 32 deletions
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66
tb/shinTest/ShinTopSpiTb.v
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@@ -384,17 +384,17 @@ initial begin
spi_csn = {`SPI_CSN_NUM{1'b1}}; //~15'b0;
#125000
//#125000
#250000
reset <= 1;
#300000
//#300000
#600000
reset <= 0;
//#20000000
#100000000000
#100000000000
#100000000000
//#5000000
#200000000000
#200000000000
#200000000000
$display("Time Out !!!");
$fclose(spidata_file);
@@ -402,7 +402,7 @@ initial begin
end
initial begin
forever begin #100000 clock <= ~clock; end
forever begin #200000 clock <= ~clock; end
end
@@ -414,14 +414,16 @@ generate
#12500
;
end
forever begin #100000 multiCLK[i] <= ~multiCLK[i]; end
forever begin #200000 multiCLK[i] <= ~multiCLK[i]; end
end
end
endgenerate
//如果频率差到 80ppm，参数是： 200016/25002/20016
//如果频率差到120ppm，参数是： 200024/25003/20024
//如果频率差到160ppm，参数是： 200032/25004/20032
initial begin
forever begin #100008 clock2 <= ~clock2; end
forever begin #200024 clock2 <= ~clock2; end
end
generate
@@ -429,10 +431,10 @@ generate
initial begin
multiCLK2[i] = 0;
for( integer j = 0; j < i; j = j + 1 ) begin
#12501
#25003
;
end
forever begin #100008 multiCLK2[i] <= ~multiCLK2[i]; end
forever begin #200024 multiCLK2[i] <= ~multiCLK2[i]; end
end
end
endgenerate
@@ -455,7 +457,7 @@ always @(negedge reset) begin
_reset_deactive <= 1'b1;
end
`define SCKFRE #800000
`define SCKFRE #1600000
reg sck = 0;
@@ -530,13 +532,13 @@ end
always @(posedge clock) begin
if( isReq & sck == 0 ) begin
isBusy <= #6250 1'b1;
transCnt <= #6250 0;
isBusy <= #12500 1'b1;
transCnt <= #12500 0;
byteCnt <= #6250 ~12'b0;
bitCnt <= #6250 ~3'b0;
byteCnt <= #12500 ~12'b0;
bitCnt <= #12500 ~3'b0;
spi_csn[idx] <= #6250 1'b0;
spi_csn[idx] <= #12500 1'b0;
exChangeRego <= txBuf[0];
end
end
@@ -583,8 +585,8 @@ always @(posedge sck) begin
exChangeRegi <= isQspi ? {exChangeRegi[3:0], qspi_mux_miso} : {exChangeRegi[6:0], spi_mux_miso};
end
end else begin
isBusy <= #6250 1'b0;
spi_csn[idx] <= #6250 1'b1;
isBusy <= #12500 1'b0;
spi_csn[idx] <= #12500 1'b1;
end
end
end
@@ -603,13 +605,13 @@ task spi_trans( input [15:0] saddress, input [7:0] scmd, input [12:0] slength,in
length <= slength + 3;
idx <= sidx;
#6250
#12500
@(negedge sck)
isReq <= 1;
@(posedge sck) #6250
@(posedge sck) #12500
isReq <= 0;
@( negedge isBusy) #1250000
@( negedge isBusy) #2500000
begin
//$fwrite(spidata_file, "------------%5t------------\n", $realtime);
$fwrite(spidata_file, "T:%t \tdev:%4d, addr:0x%02h%02h, %s, len:%4d\n",
@@ -887,13 +889,13 @@ task wait_comm_finished();
length = 8'h07;
idx = `IF_IQSPI(0);
#6250
#12500
@(negedge sck)
isReq <= 1;
@(posedge sck) #6250
@(posedge sck) #12500
isReq <= 0;
@( negedge isBusy) #1250000
@( negedge isBusy) #2500000
begin
end
@@ -907,13 +909,13 @@ task wait_comm_finished();
length = 8'h07;
idx = `IF_IQSPI(0);
#6250
#12500
@(negedge sck)
isReq <= 1;
@(posedge sck) #6250
@(posedge sck) #12500
isReq <= 0;
@( negedge isBusy) #1250000
@( negedge isBusy) #2500000
begin
end
@@ -928,7 +930,7 @@ task wait_comm_finished();
$display("error occur");
is_run = 0;
end
if (($realtime - st) >= 6250000000.0)
if (($realtime - st) >= 12500000000.0)
begin
$display("comm timeout.");
is_run = 0;
@@ -1093,7 +1095,7 @@ initial begin
`include "tc_runlist.vh"
#1250000000
#2500000000
$display("Testcase Finished! Time Out !!!");
$fclose(spidata_file);
$stop;