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所有寄存器均复位

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This commit is contained in:
RuigeLee
2025-09-02 16:22:27 +08:00
parent 0c9c52a57a
commit cbd52792a5
10 changed files with 101 additions and 110 deletions
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18
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -36,7 +36,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
val sampleReg = Wire(Vec(clkNum, Bool()))
for( i <- 0 until clkNum ) {
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2, false.B, true.B ) }
}
val sampleReg_sync = Wire(Vec(2*clkNum,Bool()))
@@ -44,11 +44,11 @@ trait CDRInMultiSample{ this: CDRInBase =>
for( i <- 0 until clkNum ){
sampleReg_sync(i) := ShiftRegister(sampleReg(i), 2)
sampleReg_sync(i) := ShiftRegister(sampleReg(i), 2, false.B, true.B)
}
for( i <- clkNum until 2*clkNum ){
sampleReg_sync(i) := ShiftRegister(sampleReg(i-clkNum), 1)
sampleReg_sync(i) := ShiftRegister(sampleReg(i-clkNum), 1, false.B, true.B)
}
/*
@@ -69,10 +69,10 @@ trait CDRInMultiSample{ this: CDRInBase =>
(sampleReg_sync(i+0) & sampleReg_sync(i+1))
}
val clearCnt = Reg(UInt(4.W))
val checkCnt = Reg(UInt(4.W))
val arbLock = Reg(UInt( (log2Ceil(2*clkNum)).W ))
val arbCali = Reg(UInt( (log2Ceil(2*clkNum)).W ))
val clearCnt = RegInit(0.U(4.W))
val checkCnt = RegInit(0.U(4.W))
val arbLock = RegInit(0.U( (log2Ceil(2*clkNum)).W ))
val arbCali = RegInit(0.U( (log2Ceil(2*clkNum)).W ))
val isLock = RegInit(false.B)
when( sampleReg_sync.reduce(_|_) === false.B ){
@@ -154,7 +154,7 @@ trait CDRInAxis{ this: CDRInBase =>
val stateNext = Wire(UInt(2.W))
val stateCurr = RegNext( stateNext, STATE_IDLE )
val bitCnt = Reg(UInt(4.W))
val bitCnt = RegInit(0.U(4.W))
val byteCnt = RegInit(0.U((12+1).W))
val checkSFD = RegInit( 0.U(20.W) )
@@ -219,7 +219,7 @@ trait CDRInAxis{ this: CDRInBase =>
val axis_valid = RegInit(false.B)
val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
val axis_tdata = RegEnable( shiftData, 0.U(8.W), bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
val axis_tuser = false.B
val axis_tlast = RegInit( false.B )

4
src/main/scala/backBoard/ebus/CDROut.scala
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@@ -36,8 +36,8 @@ class CDROut extends Module with RequireAsyncReset{
val stateCurr = RegNext( stateNext, 0.U )
val bitCnt = Reg(UInt(4.W))
val byteCnt = Reg(UInt(3.W)) //payload dont need to count
val bitCnt = RegInit(0.U(4.W))
val byteCnt = RegInit(0.U(3.W)) //payload dont need to count
val shiftData = RegInit(0.U(10.W))

2
src/main/scala/backBoard/ebus/Encryptor.scala
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@@ -13,7 +13,7 @@ class Encryptor_IO_Bundle extends Bundle{
class Encryptor extends Module{
val io: Encryptor_IO_Bundle = IO(new Encryptor_IO_Bundle)
val encryptReg = Reg(UInt(128.W))
val encryptReg = RegInit(0.U(128.W))
when( io.init.valid ){
encryptReg := io.init.bits

40
src/main/scala/backBoard/shin/Interface.scala
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@@ -397,13 +397,13 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
Seq(
//本地时钟
(addr === "h100".U ) -> cReg.timeStamp(7,0),
(addr === "h101".U ) -> RegEnable(cReg.timeStamp(15,8), isEnR & (addrr === "h100".U)),
(addr === "h102".U ) -> RegEnable(cReg.timeStamp(23,16), isEnR & (addrr === "h100".U)),
(addr === "h103".U ) -> RegEnable(cReg.timeStamp(31,24), isEnR & (addrr === "h100".U)),
(addr === "h104".U ) -> RegEnable(cReg.timeStamp(39,32), isEnR & (addrr === "h100".U)),
(addr === "h105".U ) -> RegEnable(cReg.timeStamp(47,40), isEnR & (addrr === "h100".U)),
(addr === "h106".U ) -> RegEnable(cReg.timeStamp(55,48), isEnR & (addrr === "h100".U)),
(addr === "h107".U ) -> RegEnable(cReg.timeStamp(63,56), isEnR & (addrr === "h100".U)),
(addr === "h101".U ) -> RegEnable(cReg.timeStamp(15,8), 0.U(8.W), isEnR & (addrr === "h100".U)),
(addr === "h102".U ) -> RegEnable(cReg.timeStamp(23,16), 0.U(8.W), isEnR & (addrr === "h100".U)),
(addr === "h103".U ) -> RegEnable(cReg.timeStamp(31,24), 0.U(8.W), isEnR & (addrr === "h100".U)),
(addr === "h104".U ) -> RegEnable(cReg.timeStamp(39,32), 0.U(8.W), isEnR & (addrr === "h100".U)),
(addr === "h105".U ) -> RegEnable(cReg.timeStamp(47,40), 0.U(8.W), isEnR & (addrr === "h100".U)),
(addr === "h106".U ) -> RegEnable(cReg.timeStamp(55,48), 0.U(8.W), isEnR & (addrr === "h100".U)),
(addr === "h107".U ) -> RegEnable(cReg.timeStamp(63,56), 0.U(8.W), isEnR & (addrr === "h100".U)),
//参考主站时钟
(addr === "h108".U & isSlvMode) -> sReg.deltaFinal(7,0),
@@ -429,13 +429,13 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
//校准后的时钟
(addr === "h118".U ) -> cReg.recoTimeStamp(7,0),
(addr === "h119".U ) -> RegEnable(cReg.recoTimeStamp(15,8), isEnR & (addrr === "h118".U)),
(addr === "h11a".U ) -> RegEnable(cReg.recoTimeStamp(23,16), isEnR & (addrr === "h118".U)),
(addr === "h11b".U ) -> RegEnable(cReg.recoTimeStamp(31,24), isEnR & (addrr === "h118".U)),
(addr === "h11c".U ) -> RegEnable(cReg.recoTimeStamp(39,32), isEnR & (addrr === "h118".U)),
(addr === "h11d".U ) -> RegEnable(cReg.recoTimeStamp(47,40), isEnR & (addrr === "h118".U)),
(addr === "h11e".U ) -> RegEnable(cReg.recoTimeStamp(55,48), isEnR & (addrr === "h118".U)),
(addr === "h11f".U ) -> RegEnable(cReg.recoTimeStamp(63,56), isEnR & (addrr === "h118".U)),
(addr === "h119".U ) -> RegEnable(cReg.recoTimeStamp(15,8), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h11a".U ) -> RegEnable(cReg.recoTimeStamp(23,16), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h11b".U ) -> RegEnable(cReg.recoTimeStamp(31,24), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h11c".U ) -> RegEnable(cReg.recoTimeStamp(39,32), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h11d".U ) -> RegEnable(cReg.recoTimeStamp(47,40), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h11e".U ) -> RegEnable(cReg.recoTimeStamp(55,48), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h11f".U ) -> RegEnable(cReg.recoTimeStamp(63,56), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h120".U ) -> cReg.syncCfg,
@@ -621,7 +621,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
))
datar := MuxCase( 0.U, Array(
((addrr & "hF800".U) === "h0000".U) -> RegEnable( AcquireReg(addr = addrr), isEnR ),
((addrr & "hF800".U) === "h0000".U) -> RegEnable( AcquireReg(addr = addrr), 0.U(8.W), isEnR ),
((addrr & "hF800".U) === "h0800".U) -> io.sram_r(0).datar,
((addrr & "hF800".U) === "h1000".U) -> 0.U,
((addrr & "hF800".U) === "h1800".U) -> io.sram_r(1).datar,
@@ -755,7 +755,7 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
trait InterfaceLVDSop{ this: InterfaceBase =>
io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), io.lvds.isEnR)
io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), 0.U(8.W), io.lvds.isEnR)
( 0 until 16 ).map{ i =>
@@ -974,14 +974,14 @@ trait InterfaceSync{ this: InterfaceBase =>
}
}
cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U )
cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U(64.W) )
cReg.mstDeltaTime := io.mstDeltaTime
sReg.deltaFinal := io.deltaFinal
cReg.recoTimeStamp :=
Mux(isMstMode, cReg.timeStamp,
RegNext( cReg.timeStamp + sReg.deltaFinal )
RegNext( cReg.timeStamp + sReg.deltaFinal, 0.U(64.W) )
)
sReg.slvDeltaTime := io.slvDeltaTime
@@ -1167,8 +1167,8 @@ trait InterfaceSystem{ this: InterfaceBase =>
//外部latch中断
val isLatchEvent =
(RegNext( cReg.event.latchStatus(0) ) =/= cReg.event.latchStatus(0)) |
(RegNext( cReg.event.latchStatus(1) ) =/= cReg.event.latchStatus(1))
(RegNext( cReg.event.latchStatus(0), false.B ) =/= cReg.event.latchStatus(0)) |
(RegNext( cReg.event.latchStatus(1), false.B ) =/= cReg.event.latchStatus(1))
when(isLatchEvent){
intStatus(3) := true.B

37
src/main/scala/backBoard/shin/MasterParser.scala
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@@ -30,13 +30,12 @@ class MasterParserIO extends Bundle{
abstract class MasterParserBase extends Module with RequireAsyncReset{
val io: MasterParserIO = IO(new MasterParserIO)
val txCnt = Reg(UInt(12.W))
val txLen = Reg(UInt(11.W))
val txAddr = Reg(UInt(15.W))
val rxCnt = Reg(UInt(12.W))
val rxLen = Reg(UInt(11.W))
val rxAddr = Reg(UInt(15.W))
val txCnt = RegInit(0.U(12.W))
val txLen = RegInit(0.U(11.W))
val txAddr = RegInit(0.U(15.W))
val rxCnt = RegInit(0.U(12.W))
val rxLen = RegInit(0.U(11.W))
val rxAddr = RegInit(0.U(15.W))
val reqReady = RegInit(true.B)
@@ -114,14 +113,14 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{
io.downOut.bits.tdata := Mux1H(Seq(
( txCnt < txLen ) ->
MuxCase( io.sram_r.datar, Array(
( isRplTimeStamp & ( txCnt === rplCnt0 ) ) -> RegEnable(io.cReg.timeStamp(7,0), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt1 ) ) -> RegEnable(io.cReg.timeStamp(15,8), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt2 ) ) -> RegEnable(io.cReg.timeStamp(23,16), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt3 ) ) -> RegEnable(io.cReg.timeStamp(31,24), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt4 ) ) -> RegEnable(io.cReg.timeStamp(39,32), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt5 ) ) -> RegEnable(io.cReg.timeStamp(47,40), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt6 ) ) -> RegEnable(io.cReg.timeStamp(55,48), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt7 ) ) -> RegEnable(io.cReg.timeStamp(63,56), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt0 ) ) -> RegEnable(io.cReg.timeStamp(7,0), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt1 ) ) -> RegEnable(io.cReg.timeStamp(15,8), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt2 ) ) -> RegEnable(io.cReg.timeStamp(23,16), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt3 ) ) -> RegEnable(io.cReg.timeStamp(31,24), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt4 ) ) -> RegEnable(io.cReg.timeStamp(39,32), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt5 ) ) -> RegEnable(io.cReg.timeStamp(47,40), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt6 ) ) -> RegEnable(io.cReg.timeStamp(55,48), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplTimeStamp & ( txCnt === rplCnt7 ) ) -> RegEnable(io.cReg.timeStamp(63,56), 0.U(8.W), io.downOut.fire & txCnt === 0.U ),
( isRplDeltaStamp & ( txCnt === rplCnt8 ) ) -> io.cReg.mstDeltaTime(7,0),
( isRplDeltaStamp & ( txCnt === rplCnt9 ) ) -> io.cReg.mstDeltaTime(15,8),
( isRplDeltaStamp & ( txCnt === rplCnt10 ) ) -> io.cReg.mstDeltaTime(23,16),
@@ -137,7 +136,7 @@ abstract class MasterParserBase extends Module with RequireAsyncReset{
val recCrcCheck = Reg(UInt(32.W))
val recCrcCheck = RegInit(0.U(32.W))
when( io.req ){
rxCnt := 0.U
@@ -205,12 +204,12 @@ trait MasterParserStat{ this: MasterParserBase =>
class MasterParser extends MasterParserBase
with MasterParserStat{
val deltaTimeStamp = Reg(UInt(32.W))
val deltaTimeStamp = RegInit(0.U(32.W))
// dontTouch(deltaTimeStamp)
io.deltaTimeStamp := deltaTimeStamp
val txStamps = Reg(UInt(32.W))
val pkgChkCnt = Reg(UInt(4.W))
val txStamps = RegInit(0.U(32.W))
val pkgChkCnt = RegInit(0.U(4.W))
when( io.upIn.fire & io.upIn.bits.tlast ){
pkgChkCnt := 0.U

14
src/main/scala/backBoard/shin/MstSlvSwitch.scala
View File

@@ -375,10 +375,10 @@ trait MstSlvSwitchSlave{ this: MstSlvSwitchBase =>
slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) & interface.io.intHWClr(0)
slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1) & interface.io.intHWClr(1)
io.downCDRIn.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
io.upCDRIn.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
io.downCDROut.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
io.upCDROut.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
io.downCDRIn.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0), false.B )
io.upCDRIn.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1), false.B )
io.downCDROut.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0), false.B )
io.upCDROut.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1), false.B )
interface.io.lvds <> slaveParser.io.lvds
@@ -398,7 +398,7 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
//看门狗1~16，SM监控
val isWdtSMEnable = for( _ <- 0 until 16 ) yield { RegInit(false.B) }
val wdtSMCnt = for( _ <- 0 until 16 ) yield { Reg(UInt(32.W)) }
val wdtSMCnt = for( _ <- 0 until 16 ) yield { RegInit(0.U(32.W)) }
for( i <- 0 until 8 ){
when( smUnit(i).io.enq ){
@@ -428,7 +428,7 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
//看门狗0 发送后回包是否超时
val isWdtRec2RtnEnable = RegInit(false.B)
val wdtRec2RtnCnt = Reg(UInt(32.W))
val wdtRec2RtnCnt = RegInit(0.U(32.W))
when(
(io.upCDRIn.axis.fire & io.upCDRIn.axis.bits.tlast) |
@@ -450,7 +450,7 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
interface.io.wdtTrigger(0) := wdtRec2RtnCnt === interface.io.cReg.wdtTarCnt(0)
//看门狗17
val wdtRec2RecCnt = Reg(UInt(32.W))
val wdtRec2RecCnt = RegInit(0.U(32.W))
when( interface.io.cReg.wdtEnable.extract(17) & (wdtRec2RecCnt < interface.io.cReg.wdtTarCnt(17)) ){
wdtRec2RecCnt := wdtRec2RecCnt + 1.U

56
src/main/scala/backBoard/shin/SlaveParser.scala
View File

@@ -187,11 +187,10 @@ abstract class SlaveParserBase extends Module with RequireAsyncReset{
//接收子报文
val downSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } //子报文头
val upSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) }
val downSubMsgTailInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTail) } //子报文头
val upSubMsgTailInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTail) }
val downSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { RegInit(0.U.asTypeOf(new SubMsgTxInfo)) } //子报文头
val upSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { RegInit(0.U.asTypeOf(new SubMsgTxInfo)) }
val downSubMsgTailInfo = for( _ <- 0 until 2 ) yield { RegInit(0.U.asTypeOf(new SubMsgTail) ) } //子报文头
val upSubMsgTailInfo = for( _ <- 0 until 2 ) yield { RegInit(0.U.asTypeOf(new SubMsgTail) ) }
val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 20)) } //子报文负载
@@ -485,9 +484,9 @@ trait SlaveParserRW{ this: SlaveParserBase =>
//写入 SM或寄存器空间
val addrw = Reg(UInt(15.W))
val addrw = RegInit(0.U(15.W))
val logicAddrwNext = Wire( UInt(30.W) )
val logicAddrw = RegNext(logicAddrwNext)
val logicAddrw = RegNext(logicAddrwNext, 0.U(30.W))
val isWRReg = (addrw(14,11) === "b0000".U)
val isWRSM0 = (addrw(14,11) === "b0001".U)
@@ -625,9 +624,9 @@ trait SlaveParserRW{ this: SlaveParserBase =>
val upTransLenCnt = RegInit(0.U)
val addrr = Reg(UInt(15.W))
val addrr = RegInit(0.U(15.W))
val logicAddrrNext = Wire( UInt(30.W) )
val logicAddrr = RegNext(logicAddrrNext)
val logicAddrr = RegNext(logicAddrrNext, 0.U(30.W))
val isUpLgcAddrrAcquireTrans = //是否触发地址转换
@@ -697,14 +696,14 @@ trait SlaveParserRW{ this: SlaveParserBase =>
( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) |
(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) )
)
) & ( (RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) | upRecParser.io.data.fire )
) & ( (RegNext(upRecParser.io.stateCurr, STATE_IDLE) =/= STATE_PAYLOAD_DATA) | upRecParser.io.data.fire )
val isLgcRead =
((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) |
(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) ))
)
) & ( RegNext(isUpLgcAddrrAcquireTrans) | upRecParser.io.data.fire )
) & ( RegNext(isUpLgcAddrrAcquireTrans, false.B) | upRecParser.io.data.fire )
val isLvdsEnR = isSeqRead | isLgcRead
@@ -840,20 +839,15 @@ trait SlaveParserSync{ this: SlaveParserBase =>
val downTimeStamp = Reg(UInt(64.W)) //下行本地时间戳寄存器
val upTimeStamp = Reg(UInt(64.W)) //上行本地时间戳寄存器
val mstTimeStamp = Reg(UInt(64.W)) //主站时间戳
val mstDeltaTimeStamp = Reg(UInt(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
val slvDeltaTimeStamp = Reg(UInt(32.W)); io.slvDeltaTime := slvDeltaTimeStamp //从站时间戳差值
val downTimeStamp = RegInit(0.U(64.W)) //下行本地时间戳寄存器
val upTimeStamp = RegInit(0.U(64.W)) //上行本地时间戳寄存器
val mstTimeStamp = RegInit(0.U(64.W)) //主站时间戳
val mstDeltaTimeStamp = RegInit(0.U(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
val slvDeltaTimeStamp = RegInit(0.U(32.W)); io.slvDeltaTime := slvDeltaTimeStamp //从站时间戳差值
val mstSlvDeltaTimeStamp = Reg(UInt(64.W)) //主发从接时间差(中间变量)
val deltaMstSlvDeltaTimeStamp = Reg(UInt(64.W)) //主差从差时间差(中间变量)
val deltaFinal = Reg(UInt(64.W)); io.deltaFinal := deltaFinal //当前时间戳与主站时间差
// val recoTimeStamp = Reg(UInt(64.W)) //时钟补偿寄存器
// dontTouch(recoTimeStamp)
val mstSlvDeltaTimeStamp = RegInit(0.U(64.W)) //主发从接时间差(中间变量)
val deltaMstSlvDeltaTimeStamp = RegInit(0.U(64.W)) //主差从差时间差(中间变量)
val deltaFinal = RegInit(0.U(64.W)); io.deltaFinal := deltaFinal //当前时间戳与主站时间差
// recoTimeStamp = io.timeStamp + deltaFinal
// recoTimeStamp = io.timeStamp + mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
@@ -883,7 +877,7 @@ trait SlaveParserSync{ this: SlaveParserBase =>
( ~isDownRecPing & downSubMsgHeadInfo(1).devIndex === 0.U & downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNC )
)
val syncCnt = Reg(UInt(4.W))
val syncCnt = RegInit(0.U(4.W))
when( downRecParser.io.rec.fire ){
when( isSync ){
@@ -931,7 +925,7 @@ trait SlaveParserSync{ this: SlaveParserBase =>
}
}
when( RegNext(isSync) & ~isSync ){
when( RegNext(isSync, false.B) & ~isSync ){
// deltaMstSlvDeltaTimeStamp := (mstDeltaTimeStamp - slvDeltaTimeStamp) >>> 1 //(mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1
addr64_op1 := Cat( Fill(32, mstDeltaTimeStamp(31)), mstDeltaTimeStamp) //组合逻辑
@@ -939,7 +933,7 @@ trait SlaveParserSync{ this: SlaveParserBase =>
addrConflict(2) := true.B //组合逻辑
deltaMstSlvDeltaTimeStamp := Cat(addr64_res(63),addr64_res(63,1)) //时序逻辑
} .elsewhen( RegNext(RegNext(isSync)) & ~RegNext(isSync) ){
} .elsewhen( RegNext(RegNext(isSync, false.B), false.B) & ~RegNext(isSync, false.B) ){
// deltaFinal := mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
addr64_op1 := mstSlvDeltaTimeStamp //组合逻辑
addr64_op2 := deltaMstSlvDeltaTimeStamp //组合逻辑
@@ -1020,11 +1014,11 @@ with SlaveParserProbe{
io.intHWTrig(0) := downRecParser.io.isError
io.intHWTrig(1) := upRecParser.io.isError
downRecParser.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0))
downSendGen.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0))
downRecParser.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0), false.B)
downSendGen.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0), false.B)
upRecParser.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1))
upSendGen.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1))
upRecParser.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1), false.B)
upSendGen.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1), false.B)
io.downRecStat := downRecParser.io.stat
io.upRecStat := upRecParser.io.stat

12
src/main/scala/backBoard/shin/SlaveRecParser.scala
View File

@@ -55,7 +55,7 @@ class SlaveRecParser extends Module with RequireAsyncReset{
crc.io.flush := stateCurr === STATE_IDLE | io.flush
val crcData = Reg(UInt(32.W))
val crcData = RegInit(0.U(32.W))
val isCrcPass = crc.io.crc === Cat( crcData(23,0), io.rec.bits.tdata )
when( io.rec.fire & stateCurr === STATE_CRC ){
@@ -72,12 +72,12 @@ class SlaveRecParser extends Module with RequireAsyncReset{
val lengthCnt = RegInit(0.U(12.W)) //动态计数器
val frameLenCnt = Reg(UInt(12.W)) //帧长度计数
val frameLenCnt = RegInit(0.U(12.W)) //帧长度计数
io.frameReq.valid := (stateCurr === STATE_HEADER) & (stateNext === STATE_SUBMSG_HEADER | stateNext === STATE_CRC)
val frameHeader = Reg(new FrameHeader)
val frameHeader = RegInit(0.U.asTypeOf(new FrameHeader))
io.frameReq.bits.frameLenAim := frameHeader.frameLenAim
io.frameReq.bits.frameStyle := frameHeader.frameStyle
io.frameReq.bits.frameInfo := frameHeader.frameInfo | io.rec.bits.tdata
@@ -85,8 +85,8 @@ class SlaveRecParser extends Module with RequireAsyncReset{
io.subMsgHeadReq.valid := (stateCurr === STATE_SUBMSG_HEADER) & (stateNext === STATE_PAYLOAD_DATA)
io.subMsgTailReq.valid := (stateCurr === STATE_SUBMSG_TAIL) & (stateNext =/= STATE_SUBMSG_TAIL)
val subMsgHeader = Reg(new SubMsgHeader)
val subMsgTail = Reg(new SubMsgTail)
val subMsgHeader = RegInit(0.U.asTypeOf(new SubMsgHeader))
val subMsgTail = RegInit(0.U.asTypeOf(new SubMsgTail))
io.subMsgHeadReq.bits.devIndex := subMsgHeader.devIndex
io.subMsgHeadReq.bits.style := subMsgHeader.style
@@ -182,7 +182,7 @@ class SlaveRecParser extends Module with RequireAsyncReset{
Mux( io.flush, STATE_IDLE,
Mux1H(Seq(
//必须使用上升沿触发，以避免前一帧长度超过预期
( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid) & io.rec.valid, STATE_HEADER, STATE_IDLE ),
( stateCurr === STATE_IDLE ) -> Mux( ~RegNext(io.rec.valid, false.B) & io.rec.valid, STATE_HEADER, STATE_IDLE ),
( stateCurr === STATE_HEADER ) -> Mux( io.rec.fire, Mux(io.rec.bits.tlast, STATE_ERROR,
Mux( lengthCnt === (4-1).U,
MuxCase( STATE_ERROR, Array(

10
src/main/scala/backBoard/shin/SlaveSendGen.scala
View File

@@ -66,10 +66,10 @@ class SlaveSendGen extends Module with RequireAsyncReset{
val frameInfo = Reg(new FrameHeader)
val frameInfo = RegInit(0.U.asTypeOf(new FrameHeader))
val subMsgHeadInfo = Reg(new SubMsgTxInfo)
val subMsgTailInfo = Reg(new SubMsgTail)
val subMsgHeadInfo = RegInit(0.U.asTypeOf(new SubMsgTxInfo))
val subMsgTailInfo = RegInit(0.U.asTypeOf(new SubMsgTail))
@@ -88,8 +88,8 @@ class SlaveSendGen extends Module with RequireAsyncReset{
val lengthCnt = Reg(UInt(12.W))
val frameLenCnt = Reg(UInt(12.W))
val lengthCnt = RegInit(0.U(12.W))
val frameLenCnt = RegInit(0.U(12.W))
when( io.send.fire ){
when( stateCurr === STATE_FRAME_HEADER ){

18
src/main/scala/backBoard/shin/SpiInterface.scala
View File

@@ -46,20 +46,20 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
val isSckNegedge = shiftSCK(2) & ~shiftSCK(1) //确定下降沿放数据到数据线上
val exRego = Reg(UInt(8.W))
val exRegi = Reg(UInt(8.W))
val exRego = RegInit(0.U(8.W))
val exRegi = RegInit(0.U(8.W))
val addrw = RegInit(0.U(16.W))
val addrr = RegInit(0.U(16.W))
val spiCmd = Reg(UInt(8.W))
val spiCmd = RegInit(0.U(8.W))
val isSpiWrite = spiCmd === 0.U
val isSpiRead = spiCmd === 1.U
val bitSel = Reg(UInt(3.W))
val byteSel = Reg(UInt(12.W))
val bitSel = RegInit(0.U(3.W))
val byteSel = RegInit(0.U(12.W))
io.isEnR :=
@@ -69,9 +69,7 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
io.dataw := exRegi
io.addrr := Mux( isSpiRead, addrr + 1.U, addrr )
io.addrw := addrw
// io.addrSel :=
// Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况
// val readData = RegEnable(io.datar, io.isEnR)
when( shiftCSn(2) & ~shiftCSn(1) ){
@@ -133,7 +131,7 @@ class SSpiInterface extends SpiInterfaceBase{
bitSel := bitSel + 1.U
}
val shiftMOSI = ShiftRegisters(spi.mosi, 3)
val shiftMOSI = ShiftRegisters(spi.mosi, 3, false.B, true.B)
//输入看SCK上升沿
when( isSckPosedge & ~shiftCSn(1) ){
@@ -174,7 +172,7 @@ class QSpiInterface extends SpiInterfaceBase{
bitSel := ~bitSel
}
val shiftMOSI = ShiftRegisters(qspi.mosi, 3)
val shiftMOSI = ShiftRegisters(qspi.mosi, 3, 0.U(4.W), true.B)