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所有寄存器均复位

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RuigeLee
2025-09-02 16:22:27 +08:00
parent 0c9c52a57a
commit cbd52792a5
10 changed files with 101 additions and 110 deletions
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18
src/main/scala/backBoard/shin/SpiInterface.scala
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@@ -46,20 +46,20 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
val isSckNegedge = shiftSCK(2) & ~shiftSCK(1) //确定下降沿放数据到数据线上
val exRego = Reg(UInt(8.W))
val exRegi = Reg(UInt(8.W))
val exRego = RegInit(0.U(8.W))
val exRegi = RegInit(0.U(8.W))
val addrw = RegInit(0.U(16.W))
val addrr = RegInit(0.U(16.W))
val spiCmd = Reg(UInt(8.W))
val spiCmd = RegInit(0.U(8.W))
val isSpiWrite = spiCmd === 0.U
val isSpiRead = spiCmd === 1.U
val bitSel = Reg(UInt(3.W))
val byteSel = Reg(UInt(12.W))
val bitSel = RegInit(0.U(3.W))
val byteSel = RegInit(0.U(12.W))
io.isEnR :=
@@ -69,9 +69,7 @@ abstract class SpiInterfaceBase extends Module with RequireAsyncReset{
io.dataw := exRegi
io.addrr := Mux( isSpiRead, addrr + 1.U, addrr )
io.addrw := addrw
// io.addrSel :=
// Mux( isSpiRead, addrSel + 1.U, addrSel )//覆盖三种情况
// val readData = RegEnable(io.datar, io.isEnR)
when( shiftCSn(2) & ~shiftCSn(1) ){
@@ -133,7 +131,7 @@ class SSpiInterface extends SpiInterfaceBase{
bitSel := bitSel + 1.U
}
val shiftMOSI = ShiftRegisters(spi.mosi, 3)
val shiftMOSI = ShiftRegisters(spi.mosi, 3, false.B, true.B)
//输入看SCK上升沿
when( isSckPosedge & ~shiftCSn(1) ){
@@ -174,7 +172,7 @@ class QSpiInterface extends SpiInterfaceBase{
bitSel := ~bitSel
}
val shiftMOSI = ShiftRegisters(qspi.mosi, 3)
val shiftMOSI = ShiftRegisters(qspi.mosi, 3, 0.U(4.W), true.B)