所有寄存器均复位
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RuigeLee
@@ -187,11 +187,10 @@ abstract class SlaveParserBase extends Module with RequireAsyncReset{
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//接收子报文
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val downSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) } //子报文头
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val upSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTxInfo) }
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val downSubMsgTailInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTail) } //子报文头
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val upSubMsgTailInfo = for( _ <- 0 until 2 ) yield { Reg(new SubMsgTail) }
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val downSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { RegInit(0.U.asTypeOf(new SubMsgTxInfo)) } //子报文头
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val upSubMsgHeadInfo = for( _ <- 0 until 2 ) yield { RegInit(0.U.asTypeOf(new SubMsgTxInfo)) }
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val downSubMsgTailInfo = for( _ <- 0 until 2 ) yield { RegInit(0.U.asTypeOf(new SubMsgTail) ) } //子报文头
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val upSubMsgTailInfo = for( _ <- 0 until 2 ) yield { RegInit(0.U.asTypeOf(new SubMsgTail) ) }
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val downRecFifo = for( _ <- 0 until 2 ) yield { Module(new Queue(UInt(8.W), 20)) } //子报文负载
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@@ -485,9 +484,9 @@ trait SlaveParserRW{ this: SlaveParserBase =>
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//写入 SM或寄存器空间
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val addrw = Reg(UInt(15.W))
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val addrw = RegInit(0.U(15.W))
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val logicAddrwNext = Wire( UInt(30.W) )
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val logicAddrw = RegNext(logicAddrwNext)
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val logicAddrw = RegNext(logicAddrwNext, 0.U(30.W))
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val isWRReg = (addrw(14,11) === "b0000".U)
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val isWRSM0 = (addrw(14,11) === "b0001".U)
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@@ -625,9 +624,9 @@ trait SlaveParserRW{ this: SlaveParserBase =>
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val upTransLenCnt = RegInit(0.U)
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val addrr = Reg(UInt(15.W))
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val addrr = RegInit(0.U(15.W))
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val logicAddrrNext = Wire( UInt(30.W) )
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val logicAddrr = RegNext(logicAddrrNext)
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val logicAddrr = RegNext(logicAddrrNext, 0.U(30.W))
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val isUpLgcAddrrAcquireTrans = //是否触发地址转换
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@@ -697,14 +696,14 @@ trait SlaveParserRW{ this: SlaveParserBase =>
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( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR ) ) |
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(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR ) )
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)
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) & ( (RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) | upRecParser.io.data.fire )
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) & ( (RegNext(upRecParser.io.stateCurr, STATE_IDLE) =/= STATE_PAYLOAD_DATA) | upRecParser.io.data.fire )
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val isLgcRead =
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((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
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( isUpRecPing & (upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(0).isLgcIndex & upTransLenCnt =/= 0.U ) )) |
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(~isUpRecPing & (upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIREAD | upSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR ) & ( (upSubMsgHeadInfo(1).isLgcIndex & upTransLenCnt =/= 0.U ) ))
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)
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) & ( RegNext(isUpLgcAddrrAcquireTrans) | upRecParser.io.data.fire )
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) & ( RegNext(isUpLgcAddrrAcquireTrans, false.B) | upRecParser.io.data.fire )
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val isLvdsEnR = isSeqRead | isLgcRead
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@@ -840,20 +839,15 @@ trait SlaveParserSync{ this: SlaveParserBase =>
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val downTimeStamp = Reg(UInt(64.W)) //下行本地时间戳寄存器
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val upTimeStamp = Reg(UInt(64.W)) //上行本地时间戳寄存器
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val mstTimeStamp = Reg(UInt(64.W)) //主站时间戳
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val mstDeltaTimeStamp = Reg(UInt(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
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val slvDeltaTimeStamp = Reg(UInt(32.W)); io.slvDeltaTime := slvDeltaTimeStamp //从站时间戳差值
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val downTimeStamp = RegInit(0.U(64.W)) //下行本地时间戳寄存器
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val upTimeStamp = RegInit(0.U(64.W)) //上行本地时间戳寄存器
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val mstTimeStamp = RegInit(0.U(64.W)) //主站时间戳
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val mstDeltaTimeStamp = RegInit(0.U(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
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val slvDeltaTimeStamp = RegInit(0.U(32.W)); io.slvDeltaTime := slvDeltaTimeStamp //从站时间戳差值
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val mstSlvDeltaTimeStamp = Reg(UInt(64.W)) //主发从接时间差(中间变量)
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val deltaMstSlvDeltaTimeStamp = Reg(UInt(64.W)) //主差从差时间差(中间变量)
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val deltaFinal = Reg(UInt(64.W)); io.deltaFinal := deltaFinal //当前时间戳与主站时间差
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// val recoTimeStamp = Reg(UInt(64.W)) //时钟补偿寄存器
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// dontTouch(recoTimeStamp)
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val mstSlvDeltaTimeStamp = RegInit(0.U(64.W)) //主发从接时间差(中间变量)
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val deltaMstSlvDeltaTimeStamp = RegInit(0.U(64.W)) //主差从差时间差(中间变量)
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val deltaFinal = RegInit(0.U(64.W)); io.deltaFinal := deltaFinal //当前时间戳与主站时间差
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// recoTimeStamp = io.timeStamp + deltaFinal
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// recoTimeStamp = io.timeStamp + mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
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@@ -883,7 +877,7 @@ trait SlaveParserSync{ this: SlaveParserBase =>
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( ~isDownRecPing & downSubMsgHeadInfo(1).devIndex === 0.U & downSubMsgHeadInfo(1).operator === SUBMSG_OPERATOR_SYNC )
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)
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val syncCnt = Reg(UInt(4.W))
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val syncCnt = RegInit(0.U(4.W))
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when( downRecParser.io.rec.fire ){
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when( isSync ){
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@@ -931,7 +925,7 @@ trait SlaveParserSync{ this: SlaveParserBase =>
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}
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}
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when( RegNext(isSync) & ~isSync ){
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when( RegNext(isSync, false.B) & ~isSync ){
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// deltaMstSlvDeltaTimeStamp := (mstDeltaTimeStamp - slvDeltaTimeStamp) >>> 1 //(mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1
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addr64_op1 := Cat( Fill(32, mstDeltaTimeStamp(31)), mstDeltaTimeStamp) //组合逻辑
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@@ -939,7 +933,7 @@ trait SlaveParserSync{ this: SlaveParserBase =>
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addrConflict(2) := true.B //组合逻辑
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deltaMstSlvDeltaTimeStamp := Cat(addr64_res(63),addr64_res(63,1)) //时序逻辑
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} .elsewhen( RegNext(RegNext(isSync)) & ~RegNext(isSync) ){
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} .elsewhen( RegNext(RegNext(isSync, false.B), false.B) & ~RegNext(isSync, false.B) ){
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// deltaFinal := mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
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addr64_op1 := mstSlvDeltaTimeStamp //组合逻辑
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addr64_op2 := deltaMstSlvDeltaTimeStamp //组合逻辑
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@@ -1020,11 +1014,11 @@ with SlaveParserProbe{
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io.intHWTrig(0) := downRecParser.io.isError
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io.intHWTrig(1) := upRecParser.io.isError
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downRecParser.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0))
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downSendGen.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0))
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downRecParser.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0), false.B)
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downSendGen.io.flush := RegNext(downRecParser.io.isError & io.intHWClr(0), false.B)
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upRecParser.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1))
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upSendGen.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1))
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upRecParser.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1), false.B)
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upSendGen.io.flush := RegNext(upRecParser.io.isError & io.intHWClr(1), false.B)
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io.downRecStat := downRecParser.io.stat
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io.upRecStat := upRecParser.io.stat
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