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所有寄存器均复位

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This commit is contained in:
RuigeLee
2025-09-02 16:22:27 +08:00
parent 0c9c52a57a
commit cbd52792a5
10 changed files with 101 additions and 110 deletions
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14
src/main/scala/backBoard/shin/MstSlvSwitch.scala
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@@ -375,10 +375,10 @@ trait MstSlvSwitchSlave{ this: MstSlvSwitchBase =>
slaveParser.io.intHWClr(0) := interface.io.intHWTrig(0) & interface.io.intHWClr(0)
slaveParser.io.intHWClr(1) := interface.io.intHWTrig(1) & interface.io.intHWClr(1)
io.downCDRIn.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
io.upCDRIn.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
io.downCDROut.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0) )
io.upCDROut.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1) )
io.downCDRIn.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0), false.B )
io.upCDRIn.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1), false.B )
io.downCDROut.flush := RegNext( interface.io.intHWTrig(0) & interface.io.intHWClr(0), false.B )
io.upCDROut.flush := RegNext( interface.io.intHWTrig(1) & interface.io.intHWClr(1), false.B )
interface.io.lvds <> slaveParser.io.lvds
@@ -398,7 +398,7 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
//看门狗1~16，SM监控
val isWdtSMEnable = for( _ <- 0 until 16 ) yield { RegInit(false.B) }
val wdtSMCnt = for( _ <- 0 until 16 ) yield { Reg(UInt(32.W)) }
val wdtSMCnt = for( _ <- 0 until 16 ) yield { RegInit(0.U(32.W)) }
for( i <- 0 until 8 ){
when( smUnit(i).io.enq ){
@@ -428,7 +428,7 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
//看门狗0 发送后回包是否超时
val isWdtRec2RtnEnable = RegInit(false.B)
val wdtRec2RtnCnt = Reg(UInt(32.W))
val wdtRec2RtnCnt = RegInit(0.U(32.W))
when(
(io.upCDRIn.axis.fire & io.upCDRIn.axis.bits.tlast) |
@@ -450,7 +450,7 @@ trait MstSlvSwitchWatchDog{ this: MstSlvSwitchBase =>
interface.io.wdtTrigger(0) := wdtRec2RtnCnt === interface.io.cReg.wdtTarCnt(0)
//看门狗17
val wdtRec2RecCnt = Reg(UInt(32.W))
val wdtRec2RecCnt = RegInit(0.U(32.W))
when( interface.io.cReg.wdtEnable.extract(17) & (wdtRec2RecCnt < interface.io.cReg.wdtTarCnt(17)) ){
wdtRec2RecCnt := wdtRec2RecCnt + 1.U