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所有寄存器均复位

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This commit is contained in:
RuigeLee
2025-09-02 16:22:27 +08:00
parent 0c9c52a57a
commit cbd52792a5
10 changed files with 101 additions and 110 deletions
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40
src/main/scala/backBoard/shin/Interface.scala
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@@ -397,13 +397,13 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
Seq(
//本地时钟
(addr === "h100".U ) -> cReg.timeStamp(7,0),
(addr === "h101".U ) -> RegEnable(cReg.timeStamp(15,8), isEnR & (addrr === "h100".U)),
(addr === "h102".U ) -> RegEnable(cReg.timeStamp(23,16), isEnR & (addrr === "h100".U)),
(addr === "h103".U ) -> RegEnable(cReg.timeStamp(31,24), isEnR & (addrr === "h100".U)),
(addr === "h104".U ) -> RegEnable(cReg.timeStamp(39,32), isEnR & (addrr === "h100".U)),
(addr === "h105".U ) -> RegEnable(cReg.timeStamp(47,40), isEnR & (addrr === "h100".U)),
(addr === "h106".U ) -> RegEnable(cReg.timeStamp(55,48), isEnR & (addrr === "h100".U)),
(addr === "h107".U ) -> RegEnable(cReg.timeStamp(63,56), isEnR & (addrr === "h100".U)),
(addr === "h101".U ) -> RegEnable(cReg.timeStamp(15,8), 0.U(8.W), isEnR & (addrr === "h100".U)),
(addr === "h102".U ) -> RegEnable(cReg.timeStamp(23,16), 0.U(8.W), isEnR & (addrr === "h100".U)),
(addr === "h103".U ) -> RegEnable(cReg.timeStamp(31,24), 0.U(8.W), isEnR & (addrr === "h100".U)),
(addr === "h104".U ) -> RegEnable(cReg.timeStamp(39,32), 0.U(8.W), isEnR & (addrr === "h100".U)),
(addr === "h105".U ) -> RegEnable(cReg.timeStamp(47,40), 0.U(8.W), isEnR & (addrr === "h100".U)),
(addr === "h106".U ) -> RegEnable(cReg.timeStamp(55,48), 0.U(8.W), isEnR & (addrr === "h100".U)),
(addr === "h107".U ) -> RegEnable(cReg.timeStamp(63,56), 0.U(8.W), isEnR & (addrr === "h100".U)),
//参考主站时钟
(addr === "h108".U & isSlvMode) -> sReg.deltaFinal(7,0),
@@ -429,13 +429,13 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
//校准后的时钟
(addr === "h118".U ) -> cReg.recoTimeStamp(7,0),
(addr === "h119".U ) -> RegEnable(cReg.recoTimeStamp(15,8), isEnR & (addrr === "h118".U)),
(addr === "h11a".U ) -> RegEnable(cReg.recoTimeStamp(23,16), isEnR & (addrr === "h118".U)),
(addr === "h11b".U ) -> RegEnable(cReg.recoTimeStamp(31,24), isEnR & (addrr === "h118".U)),
(addr === "h11c".U ) -> RegEnable(cReg.recoTimeStamp(39,32), isEnR & (addrr === "h118".U)),
(addr === "h11d".U ) -> RegEnable(cReg.recoTimeStamp(47,40), isEnR & (addrr === "h118".U)),
(addr === "h11e".U ) -> RegEnable(cReg.recoTimeStamp(55,48), isEnR & (addrr === "h118".U)),
(addr === "h11f".U ) -> RegEnable(cReg.recoTimeStamp(63,56), isEnR & (addrr === "h118".U)),
(addr === "h119".U ) -> RegEnable(cReg.recoTimeStamp(15,8), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h11a".U ) -> RegEnable(cReg.recoTimeStamp(23,16), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h11b".U ) -> RegEnable(cReg.recoTimeStamp(31,24), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h11c".U ) -> RegEnable(cReg.recoTimeStamp(39,32), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h11d".U ) -> RegEnable(cReg.recoTimeStamp(47,40), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h11e".U ) -> RegEnable(cReg.recoTimeStamp(55,48), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h11f".U ) -> RegEnable(cReg.recoTimeStamp(63,56), 0.U(8.W), isEnR & (addrr === "h118".U)),
(addr === "h120".U ) -> cReg.syncCfg,
@@ -621,7 +621,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
))
datar := MuxCase( 0.U, Array(
((addrr & "hF800".U) === "h0000".U) -> RegEnable( AcquireReg(addr = addrr), isEnR ),
((addrr & "hF800".U) === "h0000".U) -> RegEnable( AcquireReg(addr = addrr), 0.U(8.W), isEnR ),
((addrr & "hF800".U) === "h0800".U) -> io.sram_r(0).datar,
((addrr & "hF800".U) === "h1000".U) -> 0.U,
((addrr & "hF800".U) === "h1800".U) -> io.sram_r(1).datar,
@@ -755,7 +755,7 @@ trait InterfaceCheckSM{ this: InterfaceBase =>
trait InterfaceLVDSop{ this: InterfaceBase =>
io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), io.lvds.isEnR)
io.lvds.datar := RegEnable(AcquireReg(addr = io.lvds.addrr), 0.U(8.W), io.lvds.isEnR)
( 0 until 16 ).map{ i =>
@@ -974,14 +974,14 @@ trait InterfaceSync{ this: InterfaceBase =>
}
}
cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U )
cReg.timeStamp := RegNext( cReg.timeStamp + 1.U, 0.U(64.W) )
cReg.mstDeltaTime := io.mstDeltaTime
sReg.deltaFinal := io.deltaFinal
cReg.recoTimeStamp :=
Mux(isMstMode, cReg.timeStamp,
RegNext( cReg.timeStamp + sReg.deltaFinal )
RegNext( cReg.timeStamp + sReg.deltaFinal, 0.U(64.W) )
)
sReg.slvDeltaTime := io.slvDeltaTime
@@ -1167,8 +1167,8 @@ trait InterfaceSystem{ this: InterfaceBase =>
//外部latch中断
val isLatchEvent =
(RegNext( cReg.event.latchStatus(0) ) =/= cReg.event.latchStatus(0)) |
(RegNext( cReg.event.latchStatus(1) ) =/= cReg.event.latchStatus(1))
(RegNext( cReg.event.latchStatus(0), false.B ) =/= cReg.event.latchStatus(0)) |
(RegNext( cReg.event.latchStatus(1), false.B ) =/= cReg.event.latchStatus(1))
when(isLatchEvent){
intStatus(3) := true.B