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所有寄存器均复位

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This commit is contained in:
RuigeLee
2025-09-02 16:22:27 +08:00
parent 0c9c52a57a
commit cbd52792a5
10 changed files with 101 additions and 110 deletions
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18
src/main/scala/backBoard/ebus/CDRIn.scala
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@@ -36,7 +36,7 @@ trait CDRInMultiSample{ this: CDRInBase =>
val sampleReg = Wire(Vec(clkNum, Bool()))
for( i <- 0 until clkNum ) {
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) }
sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2, false.B, true.B ) }
}
val sampleReg_sync = Wire(Vec(2*clkNum,Bool()))
@@ -44,11 +44,11 @@ trait CDRInMultiSample{ this: CDRInBase =>
for( i <- 0 until clkNum ){
sampleReg_sync(i) := ShiftRegister(sampleReg(i), 2)
sampleReg_sync(i) := ShiftRegister(sampleReg(i), 2, false.B, true.B)
}
for( i <- clkNum until 2*clkNum ){
sampleReg_sync(i) := ShiftRegister(sampleReg(i-clkNum), 1)
sampleReg_sync(i) := ShiftRegister(sampleReg(i-clkNum), 1, false.B, true.B)
}
/*
@@ -69,10 +69,10 @@ trait CDRInMultiSample{ this: CDRInBase =>
(sampleReg_sync(i+0) & sampleReg_sync(i+1))
}
val clearCnt = Reg(UInt(4.W))
val checkCnt = Reg(UInt(4.W))
val arbLock = Reg(UInt( (log2Ceil(2*clkNum)).W ))
val arbCali = Reg(UInt( (log2Ceil(2*clkNum)).W ))
val clearCnt = RegInit(0.U(4.W))
val checkCnt = RegInit(0.U(4.W))
val arbLock = RegInit(0.U( (log2Ceil(2*clkNum)).W ))
val arbCali = RegInit(0.U( (log2Ceil(2*clkNum)).W ))
val isLock = RegInit(false.B)
when( sampleReg_sync.reduce(_|_) === false.B ){
@@ -154,7 +154,7 @@ trait CDRInAxis{ this: CDRInBase =>
val stateNext = Wire(UInt(2.W))
val stateCurr = RegNext( stateNext, STATE_IDLE )
val bitCnt = Reg(UInt(4.W))
val bitCnt = RegInit(0.U(4.W))
val byteCnt = RegInit(0.U((12+1).W))
val checkSFD = RegInit( 0.U(20.W) )
@@ -219,7 +219,7 @@ trait CDRInAxis{ this: CDRInBase =>
val axis_valid = RegInit(false.B)
val axis_tdata = RegEnable( shiftData, bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
val axis_tdata = RegEnable( shiftData, 0.U(8.W), bitCnt === 9.U & ( stateCurr === STATE_HEADER | stateCurr === STATE_PAYLOAD ) )
val axis_tuser = false.B
val axis_tlast = RegInit( false.B )

4
src/main/scala/backBoard/ebus/CDROut.scala
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@@ -36,8 +36,8 @@ class CDROut extends Module with RequireAsyncReset{
val stateCurr = RegNext( stateNext, 0.U )
val bitCnt = Reg(UInt(4.W))
val byteCnt = Reg(UInt(3.W)) //payload dont need to count
val bitCnt = RegInit(0.U(4.W))
val byteCnt = RegInit(0.U(3.W)) //payload dont need to count
val shiftData = RegInit(0.U(10.W))

2
src/main/scala/backBoard/ebus/Encryptor.scala
View File

@@ -13,7 +13,7 @@ class Encryptor_IO_Bundle extends Bundle{
class Encryptor extends Module{
val io: Encryptor_IO_Bundle = IO(new Encryptor_IO_Bundle)
val encryptReg = Reg(UInt(128.W))
val encryptReg = RegInit(0.U(128.W))
when( io.init.valid ){
encryptReg := io.init.bits