增加/修改模拟控制寄存器

src/main/scala/backBoard/shin/Interface.scala

@@ -45,7 +45,13 @@ class CommonRegisterBundle extends Bundle{
   val uniCode = UInt(64.W)
 
   val pllCtrl = UInt(32.W)
-  val xtal    = UInt(32.W)
+  val xtal    = UInt(16.W)
+  val anamuxSel = UInt(5.W)
+  val ldo2p5 = UInt(8.W)
+  val ldo1p1 = UInt(8.W)
+  val refTop = UInt(3.W)
+  val bias   = UInt(2.W)
+
 
   val softResetCode = Vec(4, UInt(8.W))
 
@@ -255,13 +261,6 @@ abstract class InterfaceBase extends Module{
         (addr === "hb".U & isSlvMode)  -> sReg.localDevIndex(15,8),
       ) ++
 
-      ((0 until 4).map{ i =>
-        (addr === ("h18".U(16.W) + i.U) ) -> cReg.pllCtrl( 8*i+7,8*i+0 )
-      }) ++
-
-      ((0 until 4).map{ i =>
-        (addr === ("h1c".U(16.W) + i.U) ) -> cReg.xtal( 8*i+7,8*i+0 )
-      }) ++
 
       Seq(
         (addr === "h20".U & isMstMode) -> Cat(mReg.rxSM, mReg.txSM, 0.U(1.W) ),
@@ -285,6 +284,22 @@ abstract class InterfaceBase extends Module{
         (addr === "h41".U ) -> cReg.softResetCode(1),
         (addr === "h42".U ) -> cReg.softResetCode(2),
         (addr === "h43".U ) -> cReg.softResetCode(3),
+      ) ++
+
+      ((0 until 4).map{ i =>
+        (addr === ("h44".U(16.W) + i.U) ) -> cReg.pllCtrl( 8*i+7,8*i+0 )
+      }) ++
+
+      ((0 until 2).map{ i =>
+        (addr === ("h48".U(16.W) + i.U) ) -> cReg.xtal( 8*i+7,8*i+0 )
+      }) ++
+
+      Seq(
+        (addr === "h50".U ) -> cReg.anamuxSel,
+        (addr === "h51".U ) -> cReg.ldo2p5,
+        (addr === "h52".U ) -> cReg.ldo1p1,
+        (addr === "h53".U ) -> cReg.refTop,
+        (addr === "h54".U ) -> cReg.bias,
 
         (addr === "h70".U ) -> cReg.intEnable(7,0),
         (addr === "h71".U ) -> cReg.intEnable(15,8),
@@ -618,20 +633,6 @@ trait InterfaceMCUop{ this: InterfaceBase =>
   cReg.busRate := RegEnable( dataw, "h55".U(8.W), isEnW & addrw === "h8".U & cReg.mstOrSlv === 0.U )
   cReg.spiSel  := RegEnable( dataw(1,0), 1.U(2.W), isEnW & addrw === "h9".U & cReg.mstOrSlv === 0.U )
 
-  cReg.pllCtrl := 
-    Cat(
-      RegEnable( dataw, "b10000000".U(8.W), isEnW & addrw === "h1b".U ),
-      RegEnable( dataw, "b00000000".U(8.W), isEnW & addrw === "h1a".U ),
-      RegEnable( dataw, "b11000000".U(8.W), isEnW & addrw === "h19".U ),
-      RegEnable( dataw, "b01011101".U(8.W), isEnW & addrw === "h18".U )
-    )
-  
-  cReg.xtal :=
-    Cat(
-      0.U(16.W),
-      RegEnable( dataw, "b00000101".U(8.W), isEnW & addrw === "h1d".U ),
-      RegEnable( dataw, "b00010101".U(8.W), isEnW & addrw === "h1c".U )
-    )
 
   mReg.txSM     := RegEnable( dataw(2,1), 0.U(2.W), isEnW & addrw === "h20".U )
   mReg.rxSM     := RegEnable( dataw(4,3), 0.U(2.W), isEnW & addrw === "h20".U )
@@ -1295,6 +1296,29 @@ trait InterfaceEvent{ this: InterfaceBase =>
   cReg.event.lvdsSMTimeStampDeq := lvdsSMTimeStampDeq
 }
 
+trait InterfaceAnalog{ this: InterfaceBase =>
+  cReg.pllCtrl := 
+    Cat(
+      RegEnable( dataw, "b10000000".U(8.W), isEnW & addrw === "h47".U ),
+      RegEnable( dataw, "b00000000".U(8.W), isEnW & addrw === "h46".U ),
+      RegEnable( dataw, "b11000000".U(8.W), isEnW & addrw === "h45".U ),
+      RegEnable( dataw, "b01011101".U(8.W), isEnW & addrw === "h44".U )
+    )
+  
+  cReg.xtal :=
+    Cat(
+      RegEnable( dataw, "b00000101".U(8.W), isEnW & addrw === "h49".U ),
+      RegEnable( dataw, "b00010101".U(8.W), isEnW & addrw === "h48".U )
+    )
+
+
+    cReg.anamuxSel := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h50".U )
+    cReg.ldo2p5 := RegEnable( dataw, "h87".U(8.W), isEnW & addrw === "h51".U )
+    cReg.ldo1p1 := RegEnable( dataw, "h87".U(8.W), isEnW & addrw === "h52".U )
+    cReg.refTop := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h53".U )
+    cReg.bias   := RegEnable( dataw, "h0".U(8.W), isEnW & addrw === "h54".U )
+}
+
 trait InterfaceStat{ this: InterfaceBase =>
 
   val statDownRecErrorCnt          = RegInit(0.U(32.W)); cReg.statDownRecErrorCnt          := statDownRecErrorCnt
@@ -1432,6 +1456,7 @@ with InterfaceStat
 with InterfaceWdt
 with InterfaceSystem
 with InterfaceEvent
+with InterfaceAnalog
 {
   cReg.hwVersion := "h1".U
   cReg.hwSerial := io.hwSerial

src/main/scala/backBoard/shin/ShinTop.scala

@@ -35,6 +35,12 @@ class ShinTopIO extends Bundle{
 
   val pllCtrl = Output(UInt(32.W))
   val xtal    = Output(UInt(12.W))
+  val anamuxSel = Output(UInt(5.W))
+  val ldo2p5 = Output(UInt(8.W))
+  val ldo1p1 = Output(UInt(8.W))
+  val refTop = Output(UInt(3.W))
+  val bias   = Output(UInt(2.W))
+
   val spiSel  = Output(UInt(2.W))
 }
 
@@ -85,7 +91,13 @@ abstract class ShinTopBase extends Module{
   io.oSync := interface.io.sync
 
   io.pllCtrl := interface.io.cReg.pllCtrl
-  io.xtal    := interface.io.cReg.xtal(11,0)
+  io.xtal    := interface.io.cReg.xtal
+  io.anamuxSel := interface.io.cReg.anamuxSel
+  io.ldo2p5    := interface.io.cReg.ldo2p5
+  io.ldo1p1    := interface.io.cReg.ldo1p1
+  io.refTop    := interface.io.cReg.refTop
+  io.bias      := interface.io.cReg.bias
+
   io.spiSel  := interface.io.cReg.spiSel
 
   val sram = Seq(