增加/修改模拟控制寄存器

src/main/scala/backBoard/shin/ShinTop.scala

@@ -35,6 +35,12 @@ class ShinTopIO extends Bundle{
 
   val pllCtrl = Output(UInt(32.W))
   val xtal    = Output(UInt(12.W))
+  val anamuxSel = Output(UInt(5.W))
+  val ldo2p5 = Output(UInt(8.W))
+  val ldo1p1 = Output(UInt(8.W))
+  val refTop = Output(UInt(3.W))
+  val bias   = Output(UInt(2.W))
+
   val spiSel  = Output(UInt(2.W))
 }
 
@@ -85,7 +91,13 @@ abstract class ShinTopBase extends Module{
   io.oSync := interface.io.sync
 
   io.pllCtrl := interface.io.cReg.pllCtrl
-  io.xtal    := interface.io.cReg.xtal(11,0)
+  io.xtal    := interface.io.cReg.xtal
+  io.anamuxSel := interface.io.cReg.anamuxSel
+  io.ldo2p5    := interface.io.cReg.ldo2p5
+  io.ldo1p1    := interface.io.cReg.ldo1p1
+  io.refTop    := interface.io.cReg.refTop
+  io.bias      := interface.io.cReg.bias
+
   io.spiSel  := interface.io.cReg.spiSel
 
   val sram = Seq(