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Merge branch 'bug56' into eb_dev

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bacon
2025-08-07 15:12:09 +08:00
parent 45bd1c6d01 0b84a1dc6f
commit cbc01a2922
2 changed files with 3 additions and 1 deletions
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2
src/main/scala/backBoard/shin/Interface.scala
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@@ -194,6 +194,7 @@ class InterfaceIO extends Bundle{
val isSMReset = Output( Vec(8, Bool()) ) val isSMReset = Output( Vec(8, Bool()) )
val latchPin = Input(Vec(2, Bool())) val latchPin = Input(Vec(2, Bool()))
val isPoReset = Output(Bool())
} }
@@ -1058,6 +1059,7 @@ trait InterfaceSystem{ this: InterfaceBase =>
if( i != 31 ) {RegInit(false.B)} else { RegInit(true.B) } if( i != 31 ) {RegInit(false.B)} else { RegInit(true.B) }
} }
cReg.intStatus := Cat( intStatus.reverse ) cReg.intStatus := Cat( intStatus.reverse )
io.isPoReset := intStatus(31)
cReg.intMode := cReg.intMode :=
Cat( Cat(

2
src/main/scala/backBoard/shin/ShinTop.scala
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@@ -452,7 +452,7 @@ with ShinTopSlave
with ShinTopWatchDog{ with ShinTopWatchDog{
when( interface.io.cReg.modeSel === false.B ){ //slave when( interface.io.cReg.modeSel === false.B ){ //slave
when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) ){ //硬件错误 when( (slaveParser.io.intHWTrig(0) | slaveParser.io.intHWTrig(1)) | interface.io.isPoReset ){ //硬件错误
downCDRIn.io.serDat := false.B downCDRIn.io.serDat := false.B
upCDRIn.io.serDat := false.B upCDRIn.io.serDat := false.B
when( slaveParser.io.isLoop ){ //回环 when( slaveParser.io.isLoop ){ //回环