diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala
index 1f3a0f1..6290a81 100644
--- a/src/main/scala/backBoard/ebus/CDRIn.scala
+++ b/src/main/scala/backBoard/ebus/CDRIn.scala
@@ -65,7 +65,7 @@ trait CDRInOverSample{ this: CDRInBase =>
 }
 
 trait CDRInMultiSample{ this: CDRInBase =>
-  
+  val testIO = IO(Output(UInt(3.W)))
   val clkNum: Int = 16
 
 
@@ -92,6 +92,8 @@ trait CDRInMultiSample{ this: CDRInBase =>
 
   syncSerDat := ShiftRegister( asyncSerDat, 2 )
 
+
+  testIO := Cat( syncSerDat, asyncSerDat, io.serDat )
 }
 
 
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 45638a1..f8aa6ad 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -36,6 +36,8 @@ class ShinTopIO extends Bundle{
   val pllCtrl = Output(UInt(32.W))
   val xtal    = Output(UInt(12.W))
   val spiSel  = Output(UInt(2.W))
+
+  val testIO = Output(UInt(12.W))
 }
 
 
@@ -73,7 +75,11 @@ abstract class ShinTopBase extends Module{
   interface.io.intTransEnd(3) := upCDROut.io.axis.fire   & upCDROut.io.axis.bits.tlast
 
   io.ledTest := RegNext( Cat(slaveParser.io.intHWTrig(0), slaveParser.io.intHWTrig(1)) )
-  
+
+  io.testIO := Cat(
+    upCDROut.io.serDat, upCDRIn.testIO, downCDROut.io.serDat, downCDRIn.testIO, clock.asBool
+  )
+
   io.isSoftReset := interface.io.isSoftReset
   io.interrupt   := interface.io.interrupt