diff --git a/src/main/scala/backBoard/shin/Interface.scala b/src/main/scala/backBoard/shin/Interface.scala
index fb034aa..7cee3a9 100644
--- a/src/main/scala/backBoard/shin/Interface.scala
+++ b/src/main/scala/backBoard/shin/Interface.scala
@@ -3,6 +3,19 @@ package BACK
 import chisel3._
 import chisel3.util._
 
+
+class EBMMU_Bundle extends Bundle{
+  val lAddr = UInt(30.W)
+  val pAddr = UInt(16.W)
+  val length = UInt(16.W)
+  val op = UInt(8.W)
+  val isEnable = Bool()
+
+  def EBMMU_OP_RD = op === 1.U
+  def EBMMU_OP_WR = op === 2.U
+  def EBMMU_OP_RW = op === 3.U
+}
+
 class CommonRegisterBundle extends Bundle{
   val mstOrSlv  = UInt(2.W)
   def modeSel:Bool = mstOrSlv === "h1".U
@@ -72,13 +85,7 @@ class SlaveRegisterBundle extends Bundle{
   // val nodeSetAddr = UInt(16.W)
 
 
-  // val ebmmu = Vec(8, new Bundle{
-  //   val logicAddr = UInt(32.W)
-  //   val length = UInt(16.W)
-  //   val phyAddr = UInt(32.W)
-  //   val op = UInt(2.W)
-  //   val enable = Bool()
-  // })
+  val ebmmu = Vec(8, new EBMMU_Bundle)
 
   // val intStatus = UInt(16.W)
   // val mb = Vec(8, new Bundle{
@@ -364,6 +371,21 @@ abstract class InterfaceBase extends Module{
       ( 0 until 128 ).map{ i =>
         ( addr === ("h180".U(16.W) + i.U )   ) -> cReg.custom(i)
       } ++
+      ( 0 until 8 ).map{ i => Seq(
+        ( ( addr === ( "h200".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr( 7, 0),
+        ( ( addr === ( "h201".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(15, 8),
+        ( ( addr === ( "h202".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(23,16),
+        ( ( addr === ( "h203".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).lAddr(29,24),
+
+        ( ( addr === ( "h204".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).pAddr( 7, 0),
+        ( ( addr === ( "h205".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).pAddr(15, 8),
+
+        ( ( addr === ( "h206".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).length( 7, 0),
+        ( ( addr === ( "h207".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).length(15, 8),
+
+        ( ( addr === ( "h208".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).op,
+        ( ( addr === ( "h209".U(16.W) + (10*i).U) ) & isSlvMode ) -> sReg.ebmmu(i).isEnable,
+      )}.reduce(_++_) ++
       ( 0 until 8 ).map{ i =>
         ( addr === ("h302".U(16.W) + (i*4).U) )  -> cReg.smTrigLen(i)(7,0)
       } ++
@@ -725,6 +747,33 @@ trait InterfaceLVDSop{ this: InterfaceBase =>
       }      
     }
   }
+
+
+  ( 0 until 8 ).map{ i =>
+    sReg.ebmmu(i).lAddr := Cat(
+      RegEnable( io.lvds.dataw(5,0), 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h203".U(16.W) + (10*i).U )) ),
+      RegEnable( io.lvds.dataw,      0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h202".U(16.W) + (10*i).U )) ),
+      RegEnable( io.lvds.dataw,      0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h201".U(16.W) + (10*i).U )) ),
+      RegEnable( io.lvds.dataw,      0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h200".U(16.W) + (10*i).U )) ),
+    )
+
+    sReg.ebmmu(i).pAddr := Cat(
+      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h205".U(16.W) + (10*i).U )) ),
+      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h204".U(16.W) + (10*i).U )) ),
+    )
+
+    sReg.ebmmu(i).length := Cat(
+      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h207".U(16.W) + (10*i).U )) ),
+      RegEnable( io.lvds.dataw, 0.U, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h206".U(16.W) + (10*i).U )) ),
+    )
+
+    sReg.ebmmu(i).op :=
+      RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h208".U(16.W) + (10*i).U )) )
+
+    sReg.ebmmu(i).isEnable :=
+      RegEnable( io.lvds.dataw.extract(0), false.B, io.lvds.isEnW & isSlvMode & (io.lvds.addrw === ( "h209".U(16.W) + (10*i).U )) )
+  }
+
 }
 
 trait InterfaceSync{ this: InterfaceBase =>
diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala
index 8796ce8..0476b00 100644
--- a/src/main/scala/backBoard/shin/ShinTop.scala
+++ b/src/main/scala/backBoard/shin/ShinTop.scala
@@ -329,6 +329,7 @@ trait ShinTopSlave{ this: ShinTopBase =>
   }
 
   slaveParser.io.cReg := interface.io.cReg
+  slaveParser.io.sReg := interface.io.sReg
 
 
   when( interface.io.cReg.modeSel === false.B ){
diff --git a/src/main/scala/backBoard/shin/SlaveParser.scala b/src/main/scala/backBoard/shin/SlaveParser.scala
index 9113e9d..23c08b1 100644
--- a/src/main/scala/backBoard/shin/SlaveParser.scala
+++ b/src/main/scala/backBoard/shin/SlaveParser.scala
@@ -17,6 +17,9 @@ class SubMsgHeader extends Bundle{
   val operator = UInt(4.W)  //子报文命令类型
   val length   = UInt(12.W) //子报文负载长度
   val workCnt  = UInt(16.W) //子报文工作计数
+
+  def isSeqIndex = style === 0.U
+  def isLgcIndex = style === 2.U
 }
 
 
@@ -65,6 +68,7 @@ class SlaveParserIO extends Bundle{
   val isLoop = Output(Bool())
 
   val cReg = Input(new CommonRegisterBundle)
+  val sReg = Input(new SlaveRegisterBundle)
 
   val lvds  = new RegAccessInterfaceIO
 
@@ -75,6 +79,8 @@ class SlaveParserIO extends Bundle{
 abstract class SlaveParserBase extends Module{
   val io: SlaveParserIO = IO(new SlaveParserIO)
 
+  val sReg = io.sReg
+
 
 
   val FRAME_STYLE_COMMON = 0.U
@@ -376,6 +382,16 @@ trait SlaveParserIndex{ this: SlaveParserBase =>
 
 trait SlaveParserRW{ this: SlaveParserBase =>
 
+  // val isSeqIndexMatch = 
+  //   (downRecParser.io.subMsgReq.bits.isSeqIndex & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex)
+
+  // val downLgcAddress  = Cat( downRecParser.io.subMsgReq.bits.devIndex, downRecParser.io.subMsgReq.bits.address )
+  // val isLgcIndexMatch = 
+  //   (downRecParser.io.subMsgReq.bits.isLgcIndex &
+
+
+
+
   //下行接收
   when( downRecParser.io.subMsgReq.fire ){
     when( isDownRecPing ){
@@ -403,32 +419,84 @@ trait SlaveParserRW{ this: SlaveParserBase =>
   //写入 SM或寄存器空间
 
   val addrw = Reg(UInt(15.W))
+  val logicAddrwNext = Wire( UInt(30.W) )
+  val logicAddrw = RegNext(logicAddrwNext)
 
   val isWRReg = (addrw(14,11) === "b0000".U)
-  val isWRSM0      = (addrw(14,11) === "b0001".U)
-  val isWRSM2      = (addrw(14,11) === "b0011".U)
-  val isWRSM4      = (addrw(14,11) === "b0101".U)
-  val isWRSM6      = (addrw(14,11) === "b0111".U)
+  val isWRSM0 = (addrw(14,11) === "b0001".U)
+  val isWRSM2 = (addrw(14,11) === "b0011".U)
+  val isWRSM4 = (addrw(14,11) === "b0101".U)
+  val isWRSM6 = (addrw(14,11) === "b0111".U)
 
 
   val isWrite = (downRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & ( //req fire 后 已经反相
-    ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE)   | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR  ) ) & (downSubMsgInfo(0).devIndex === localDevIndex)) |
-    (  isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE)   | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR  ) ) & (downSubMsgInfo(1).devIndex === localDevIndex)) |
+    ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIWRITE)   | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR  ) ) & ( (downSubMsgInfo(0).isSeqIndex & downSubMsgInfo(0).devIndex === localDevIndex) || downSubMsgInfo(0).isLgcIndex) ) |
+    (  isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIWRITE)   | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR  ) ) & ( (downSubMsgInfo(1).isSeqIndex & downSubMsgInfo(1).devIndex === localDevIndex) || downSubMsgInfo(1).isLgcIndex) ) |
     ( ~isDownRecPing & ( (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR) )                                                 ) |
     (  isDownRecPing & ( (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDWRITE) | (downSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR) )                                                 )
   )
 
-  when( downRecParser.io.subMsgReq.fire & (
-    downRecParser.io.subMsgReq.bits.devIndex === localDevIndex |
-    downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE |
-    downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR
-    )
-  ){
-    addrw := downRecParser.io.subMsgReq.bits.address
-  } .elsewhen( isWrite & downRecParser.io.data.fire ){
-    addrw := addrw + 1.U
+  val downTransLenCnt = RegInit(0.U)
+
+  val isDownLgcAddrwAcquireTrans = //是否触发地址转换
+    (downTransLenCnt === 0.U) & ( (0 until 8).map{ i =>
+      sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)
+    }.reduce(_|_))
+
+  val acquireDownPhyAddrw = Mux1H( //选择一个ebmmu
+    (0 until 8).map{ i =>
+      (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) ->
+      sReg.ebmmu(i).pAddr
+    }
+  )
+
+  val acquireDownTransLen = Mux1H( //选择一个ebmmu
+    (0 until 8).map{ i =>
+      (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_WR || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) ->
+      sReg.ebmmu(i).length
+    }
+  )
+
+  when( isDownLgcAddrwAcquireTrans ){ //装填计数器
+    downTransLenCnt := acquireDownTransLen
+  } .elsewhen( downRecParser.io.data.fire & downTransLenCnt =/= 0.U){
+    downTransLenCnt := downTransLenCnt - 1.U
   }
 
+  //组合逻辑
+  when( downRecParser.io.subMsgReq.fire & (
+    (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex 
+  )){//组合逻辑
+    logicAddrwNext := Cat( downRecParser.io.subMsgReq.bits.devIndex, downRecParser.io.subMsgReq.bits.address )
+  } .elsewhen( isWrite & downRecParser.io.data.fire ){//组合逻辑
+    logicAddrwNext := logicAddrw + 1.U
+  } .otherwise{//组合逻辑
+    logicAddrwNext := logicAddrw
+  }
+
+
+  when( downRecParser.io.subMsgReq.fire ){ //子包头装填
+    when(
+      ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE   | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isSeqIndex & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) |
+      (  downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR )
+    ){ //常规寻址
+      addrw := downRecParser.io.subMsgReq.bits.address
+    } .elsewhen( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex ){ //逻辑寻址
+      addrw := acquireDownPhyAddrw
+    }
+  } .elsewhen( isWrite & downRecParser.io.data.fire ){
+    when(
+      ( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE   | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isSeqIndex & downRecParser.io.subMsgReq.bits.devIndex === localDevIndex ) |
+      (  downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR )
+    ){
+      addrw := addrw + 1.U
+    } .elsewhen( (downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIWRITE | downRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & downRecParser.io.subMsgReq.bits.isLgcIndex ){
+      addrw := Mux( downTransLenCnt === 0.U, Mux(isDownLgcAddrwAcquireTrans, acquireDownPhyAddrw, 0.U), addrw + 1.U )
+    }
+  }
+
+
+
 
   io.lvds.isEnW   := isWrite & isWRReg & downRecParser.io.data.fire
   io.lvds.dataw   := downRecParser.io.data.bits
@@ -453,10 +521,6 @@ trait SlaveParserRW{ this: SlaveParserBase =>
   
 
 
-  // val SUBMSG_OPERATOR_BOARDREAD  = "hd".U
-  // val SUBMSG_OPERATOR_BOARDWRITE = "he".U
-  // val SUBMSG_OPERATOR_BOARDRDWR  = "hf".U
-
 
   //上行接收
   when( upRecParser.io.subMsgReq.fire ){
@@ -487,14 +551,55 @@ trait SlaveParserRW{ this: SlaveParserBase =>
   //读出uSM  
   val isRead = 
     ((upRecParser.io.stateCurr === STATE_PAYLOAD_DATA) & (
-      (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR   ) & upSubMsgInfo(0).devIndex === localDevIndex) |
-      ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR   ) & upSubMsgInfo(1).devIndex === localDevIndex) |
+      (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR   ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) || upSubMsgInfo(0).isLgcIndex)) |
+      ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR   ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) || upSubMsgInfo(1).isLgcIndex)) |
       (~isUpRecPing & (upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR )                                             ) |
       ( isUpRecPing & (upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR )                                             )
     )
   )
 
   val addrr = Reg(UInt(15.W))  
+  val logicAddrrNext = Wire( UInt(30.W) )
+  val logicAddrr = RegNext(logicAddrrNext)
+
+  val upTransLenCnt = RegInit(0.U)
+
+  val isUpLgcAddrwAcquireTrans = //是否触发地址转换
+    (upTransLenCnt === 0.U) & ( (0 until 8).map{ i =>
+      sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)
+    }.reduce(_|_))
+
+  val acquireUpPhyAddrw = Mux1H( //选择一个ebmmu
+    (0 until 8).map{ i =>
+      (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) ->
+      sReg.ebmmu(i).pAddr
+    }
+  )
+
+  val acquireUpTransLen = Mux1H( //选择一个ebmmu
+    (0 until 8).map{ i =>
+      (sReg.ebmmu(i).isEnable & (sReg.ebmmu(i).EBMMU_OP_RD || sReg.ebmmu(i).EBMMU_OP_RW) & (logicAddrwNext === sReg.ebmmu(i).lAddr)) ->
+      sReg.ebmmu(i).length
+    }
+  )
+
+  when( isUpLgcAddrwAcquireTrans ){ //装填计数器
+    upTransLenCnt := acquireUpTransLen
+  } .elsewhen( upRecParser.io.data.fire & upTransLenCnt =/= 0.U){
+    upTransLenCnt := upTransLenCnt - 1.U
+  }
+
+  //组合逻辑
+  when( upRecParser.io.subMsgReq.fire & (
+    (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex 
+  )){//组合逻辑
+    logicAddrrNext := Cat( upRecParser.io.subMsgReq.bits.devIndex, upRecParser.io.subMsgReq.bits.address )
+  } .elsewhen( isRead & upRecParser.io.data.fire ){//组合逻辑
+    logicAddrrNext := logicAddrw + 1.U
+  } .otherwise{//组合逻辑
+    logicAddrrNext := logicAddrr
+  }
+
 
   val isRDReg = addrr(14,11) === "b0000".U
   val isRDSM1 = addrr(14,11) === "b0010".U
@@ -505,15 +610,24 @@ trait SlaveParserRW{ this: SlaveParserBase =>
   val isLvdsEnR = isRead & ( ((RegNext(upRecParser.io.stateCurr) =/= STATE_PAYLOAD_DATA) & (upRecParser.io.stateCurr === STATE_PAYLOAD_DATA)) |
       upRecParser.io.data.fire )
 
-  when( upRecParser.io.subMsgReq.fire & (
-      upRecParser.io.subMsgReq.bits.devIndex === localDevIndex |
-      upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD |
-      upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR
-    )
-  ){
-    addrr := upRecParser.io.subMsgReq.bits.address
+  when( upRecParser.io.subMsgReq.fire){
+    when(
+      ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD   | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR  ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) |
+      ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR)
+    ){
+      addrr := upRecParser.io.subMsgReq.bits.address
+    } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){
+      addrr := acquireUpPhyAddrw
+    }
   } .elsewhen( isLvdsEnR ){
-    addrr := addrr + 1.U
+    when( 
+      ((upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD   | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR  ) & (upRecParser.io.subMsgReq.bits.isSeqIndex & upRecParser.io.subMsgReq.bits.devIndex === localDevIndex)) |
+      ( upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_BOARDRDWR)
+    ){
+      addrr := addrr + 1.U
+    } .elsewhen( (upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIREAD | upRecParser.io.subMsgReq.bits.operator === SUBMSG_OPERATOR_UNIRDWR) & upRecParser.io.subMsgReq.bits.isLgcIndex ){
+      addrr := Mux( upTransLenCnt === 0.U, Mux(isUpLgcAddrwAcquireTrans, acquireUpPhyAddrw, 0.U), addrr + 1.U )
+    }
   }
 
   val upStreamData = Mux1H(Seq(
@@ -529,7 +643,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
     upRecFifo(0).io.enq.valid := upRecParser.io.data.valid
     upRecFifo(0).io.enq.bits  := 
       Mux( 
-           ( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR   ) & upSubMsgInfo(0).devIndex === localDevIndex, upStreamData,
+           ( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_UNIRDWR   ) & ((upSubMsgInfo(0).isSeqIndex & upSubMsgInfo(0).devIndex === localDevIndex) | upSubMsgInfo(0).isLgcIndex), upStreamData,
         Mux( upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(0).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits,
           upRecParser.io.data.bits )
       )
@@ -544,7 +658,7 @@ trait SlaveParserRW{ this: SlaveParserBase =>
     upRecFifo(1).io.enq.valid := upRecParser.io.data.valid
     upRecFifo(1).io.enq.bits  :=
       Mux( 
-           ( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR   ) & upSubMsgInfo(1).devIndex === localDevIndex, upStreamData,
+           ( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIREAD   | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_UNIRDWR   ) & ((upSubMsgInfo(1).isSeqIndex & upSubMsgInfo(1).devIndex === localDevIndex) | upSubMsgInfo(1).isLgcIndex), upStreamData,
         Mux( upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDREAD | upSubMsgInfo(1).operator === SUBMSG_OPERATOR_BOARDRDWR, upStreamData | upRecParser.io.data.bits,
           upRecParser.io.data.bits
         )
diff --git a/tb/shinTest/ShinTopSpiTb.v b/tb/shinTest/ShinTopSpiTb.v
index a96eac1..301bf87 100644
--- a/tb/shinTest/ShinTopSpiTb.v
+++ b/tb/shinTest/ShinTopSpiTb.v
@@ -18,8 +18,8 @@
 
 `define ENABLE_SYNC_TEST
 `define ENABLE_SYNC_SIG0_TEST
-`define ENABLE_SYNC_SIG1_TEST
-`define ENABLE_RESET_TEST
+//`define ENABLE_SYNC_SIG1_TEST
+//`define ENABLE_RESET_TEST
 
 module ShinTopSpiTb(
 
@@ -1295,7 +1295,19 @@ initial begin
     
   end
 `endif
+  begin:RESET_SYSTEM_TEST
+    _t_start = $realtime;
+    #1000
 
+    $fdisplay(spidata_file, "\n\n测试用例：EBMMU测试");
+
+    `include "ebmmu_settings.vh"
+
+    `include "ebmmu_read.vh"
+
+    _t_end = $realtime;
+    $fdisplay(spidata_file, "该测试用例运行时间：%t\n", _t_end - _t_start);
+  end
 
 
   #1000000
diff --git a/tb/shinTest/gen_pkt.py b/tb/shinTest/gen_pkt.py
index ba6b18f..1cc00b1 100755
--- a/tb/shinTest/gen_pkt.py
+++ b/tb/shinTest/gen_pkt.py
@@ -725,7 +725,7 @@ if __name__ == '__main__':
     data[19] = '''(_temp_time >> 24) & 8'hff'''
     
     data[24] = 0x00 #地址0x138, sync周期 4B
-    data[25] = 0x04 #地址0x139
+    data[25] = 0x04 #地址0x139genPkt.addBeforeExc(
     
     data[28] = 0x0 #sync1偏移
     data[29] = 0x0
@@ -844,7 +844,113 @@ if __name__ == '__main__':
 
 
     
-    
-    
+    #-------------------------------------------------------------------------
+    #>>>>>>设置EB-MMU
+    genPkt.clean()
+    genPkt.setPktType(0)
+
+    #subPkt参数：索引、索引类型、地址、命令、长度、数据   
+    data = [0,] * 30
+
+    data[0] = 0x00
+    data[1] = 0x00
+    data[2] = 0x00
+    data[3] = 0x10
+
+    data[4] = 0x00
+    data[5] = 0x02
+
+    data[6] = 0x0a
+    data[7] = 0x00
+
+    data[8] = 0x03
+    data[9] = 0x01
+
+    genPkt.addSubPkt(0x1, 0, 0x0200, 0x1, 10, data)
+
+
+    data = [0,] * 30
+    data[0] = 0x0a
+    data[1] = 0x00
+    data[2] = 0x00
+    data[3] = 0x10
+
+    data[4] = 0x00
+    data[5] = 0x02
+
+    data[6] = 0x0a
+    data[7] = 0x00
+
+    data[8] = 0x03
+    data[9] = 0x01
+    genPkt.addSubPkt(0x2, 0, 0x0200, 0x1, 10, data)
+
+
+    data = [0,] * 30
+
+    data[0] = 0x14
+    data[1] = 0x00
+    data[2] = 0x00
+    data[3] = 0x10
+
+    data[4] = 0x00
+    data[5] = 0x02
+
+    data[6] = 0x0a
+    data[7] = 0x00
+
+    data[8] = 0x03
+    data[9] = 0x01
+    genPkt.addSubPkt(0x3, 0, 0x0200, 0x1, 10, data)
+
+    data = [0,] * 30
+
+    data[0] = 0x1e
+    data[1] = 0x00
+    data[2] = 0x00
+    data[3] = 0x10
+
+    data[4] = 0x00
+    data[5] = 0x02
+
+    data[6] = 0x0a
+    data[7] = 0x00
+
+    data[8] = 0x03
+    data[9] = 0x01
+    genPkt.addSubPkt(0x4, 0, 0x0200, 0x1, 10, data)
+
+
+    gen_file_def = "ebmmu_settings"
+    sm_idx = 0
+
+    genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
+                       +genWriteTransPktCode(gen_file_def, sm_idx)
+                       +genTrgTransPktCode(gen_file_def, sm_idx)
+                       +genReadAckPktCode(gen_file_def, sm_idx))
+
+    genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
+    
+
+    #-------------------------------------------------------------------------
+    #>>>>>>设置EB-MMU
+    genPkt.clean()
+    genPkt.setPktType(0)
+
+    #subPkt参数：索引、索引类型、地址、命令、长度、数据   
+    data = [0,] * 40
+
+    genPkt.addSubPkt(0x1000, 2, 0x0000, 0x0, 40, data)
+
+    gen_file_def = "ebmmu_read"
+    sm_idx = 0
+
+    genPkt.addAfterExc(genWriteTransLenCode(gen_file_def, sm_idx)
+                       +genWriteTransPktCode(gen_file_def, sm_idx)
+                       +genTrgTransPktCode(gen_file_def, sm_idx)
+                       +genReadAckPktCode(gen_file_def, sm_idx))
+
+    genPkt.gen("./generated/shin/%s.vh"%(gen_file_def, ), 1)
+