增加sim cdr clk的生成python文件,支持在Makefile中动态生成相位和时钟偏差

tb/shinTest/SimCDRTb.v

@@ -25,7 +25,8 @@ module SimCDRTb(
     initial begin
         forever begin #8000000 clock <= ~clock; end
     end
-
+    
+    /*
     generate
     for( genvar i = 0; i < 16; i = i + 1 ) begin
         initial begin
@@ -38,6 +39,9 @@ module SimCDRTb(
         end
     end  
     endgenerate
+    */
+
+    `include "simCdrClk.vh"
 
     reg [7:0] data;
     wire success;