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Merge branch 'mp_eb_dev' into feature/liftCdr

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This commit is contained in:
Ruige Lee
2025-08-26 17:07:58 +08:00
parent 72fe230200 b821571218
commit c6bd7902e7
2 changed files with 58 additions and 30 deletions
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42
src/main/scala/backBoard/shin/Interface.scala
View File

@@ -138,7 +138,7 @@ class SlaveRegisterBundle extends Bundle{
val slvDeltaTime = UInt(32.W) //从站时间戳差值
val deltaFinal = UInt(32.W) //当前时间戳与主站时间差
val deltaFinal = UInt(64.W) //当前时间戳与主站时间差
@@ -183,7 +183,7 @@ class InterfaceIO extends Bundle{
val slvDeltaTime = Input(UInt(32.W)) //从站时间戳差值
val mstDeltaTime = Input(UInt(32.W))
val deltaFinal = Input(UInt(32.W))
val deltaFinal = Input(UInt(64.W))
val sync = Output(Vec(4, Bool()))
@@ -379,23 +379,23 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
Seq(
//本地时钟
(addr === "h100".U ) -> cReg.timeStamp(7,0),
(addr === "h101".U ) -> cReg.timeStamp(15,8),
(addr === "h102".U ) -> cReg.timeStamp(23,16),
(addr === "h103".U ) -> cReg.timeStamp(31,24),
(addr === "h104".U ) -> cReg.timeStamp(39,32),
(addr === "h105".U ) -> cReg.timeStamp(47,40),
(addr === "h106".U ) -> cReg.timeStamp(55,48),
(addr === "h107".U ) -> cReg.timeStamp(63,56),
(addr === "h101".U ) -> RegEnable(cReg.timeStamp(15,8), isEnR & (addrr === "h100".U)),
(addr === "h102".U ) -> RegEnable(cReg.timeStamp(23,16), isEnR & (addrr === "h100".U)),
(addr === "h103".U ) -> RegEnable(cReg.timeStamp(31,24), isEnR & (addrr === "h100".U)),
(addr === "h104".U ) -> RegEnable(cReg.timeStamp(39,32), isEnR & (addrr === "h100".U)),
(addr === "h105".U ) -> RegEnable(cReg.timeStamp(47,40), isEnR & (addrr === "h100".U)),
(addr === "h106".U ) -> RegEnable(cReg.timeStamp(55,48), isEnR & (addrr === "h100".U)),
(addr === "h107".U ) -> RegEnable(cReg.timeStamp(63,56), isEnR & (addrr === "h100".U)),
//参考主站时钟
(addr === "h108".U & isSlvMode) -> sReg.deltaFinal(7,0),
(addr === "h109".U & isSlvMode) -> sReg.deltaFinal(15,8),
(addr === "h10a".U & isSlvMode) -> sReg.deltaFinal(23,16),
(addr === "h10b".U & isSlvMode) -> sReg.deltaFinal(31,24),
// (addr === "h10c".U & isSlvMode) -> sReg.deltaFinal(39,32),
// (addr === "h10d".U & isSlvMode) -> sReg.deltaFinal(47,40),
// (addr === "h10e".U & isSlvMode) -> sReg.deltaFinal(55,48),
// (addr === "h10f".U & isSlvMode) -> sReg.deltaFinal(63,56),
(addr === "h10c".U & isSlvMode) -> sReg.deltaFinal(39,32),
(addr === "h10d".U & isSlvMode) -> sReg.deltaFinal(47,40),
(addr === "h10e".U & isSlvMode) -> sReg.deltaFinal(55,48),
(addr === "h10f".U & isSlvMode) -> sReg.deltaFinal(63,56),
//主站发送接收时间差
(addr === "h110".U ) -> cReg.mstDeltaTime(7,0),
@@ -411,13 +411,13 @@ abstract class InterfaceBase extends Module with RequireAsyncReset{
//校准后的时钟
(addr === "h118".U ) -> cReg.recoTimeStamp(7,0),
(addr === "h119".U ) -> cReg.recoTimeStamp(15,8),
(addr === "h11a".U ) -> cReg.recoTimeStamp(23,16),
(addr === "h11b".U ) -> cReg.recoTimeStamp(31,24),
(addr === "h11c".U ) -> cReg.recoTimeStamp(39,32),
(addr === "h11d".U ) -> cReg.recoTimeStamp(47,40),
(addr === "h11e".U ) -> cReg.recoTimeStamp(55,48),
(addr === "h11f".U ) -> cReg.recoTimeStamp(63,56),
(addr === "h119".U ) -> RegEnable(cReg.recoTimeStamp(15,8), isEnR & (addrr === "h118".U)),
(addr === "h11a".U ) -> RegEnable(cReg.recoTimeStamp(23,16), isEnR & (addrr === "h118".U)),
(addr === "h11b".U ) -> RegEnable(cReg.recoTimeStamp(31,24), isEnR & (addrr === "h118".U)),
(addr === "h11c".U ) -> RegEnable(cReg.recoTimeStamp(39,32), isEnR & (addrr === "h118".U)),
(addr === "h11d".U ) -> RegEnable(cReg.recoTimeStamp(47,40), isEnR & (addrr === "h118".U)),
(addr === "h11e".U ) -> RegEnable(cReg.recoTimeStamp(55,48), isEnR & (addrr === "h118".U)),
(addr === "h11f".U ) -> RegEnable(cReg.recoTimeStamp(63,56), isEnR & (addrr === "h118".U)),
(addr === "h120".U ) -> cReg.syncCfg,
@@ -963,7 +963,7 @@ trait InterfaceSync{ this: InterfaceBase =>
sReg.deltaFinal := io.deltaFinal
cReg.recoTimeStamp :=
Mux(isMstMode, cReg.timeStamp,
RegNext( cReg.timeStamp + Cat( Fill(32, sReg.deltaFinal.extract(31)), sReg.deltaFinal ) )
RegNext( cReg.timeStamp + sReg.deltaFinal )
)
sReg.slvDeltaTime := io.slvDeltaTime

46
src/main/scala/backBoard/shin/SlaveParser.scala
View File

@@ -66,7 +66,7 @@ class SlaveParserIO extends Bundle{
val mstDeltaTimeStamp = Output(UInt(32.W))
val slvDeltaTime = Output(UInt(32.W))
val deltaFinal = Output(UInt(32.W))
val deltaFinal = Output(UInt(64.W))
val isLoop = Output(Bool())
@@ -812,6 +812,14 @@ trait SlaveParserRW{ this: SlaveParserBase =>
trait SlaveParserSync{ this: SlaveParserBase =>
val addr64_op1 = WireDefault( 0.U(64.W) )
val addr64_op2 = WireDefault( 0.U(64.W) )
def subOp2(x:UInt) = ~x + 1.U
val addr64_res = addr64_op1 + addr64_op2
val addrConflict = WireDefault(VecInit(Seq.fill(4){false.B}))
assert( PopCount(addrConflict) <= 1.U )
//下行接收
when( downRecParser.io.subMsgTailReq.fire ){
@@ -837,9 +845,9 @@ trait SlaveParserSync{ this: SlaveParserBase =>
val mstDeltaTimeStamp = Reg(UInt(32.W)); io.mstDeltaTimeStamp := mstDeltaTimeStamp //主站时间戳差值
val slvDeltaTimeStamp = Reg(UInt(32.W)); io.slvDeltaTime := slvDeltaTimeStamp //从站时间戳差值
val mstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主发从接时间差(中间变量)
val deltaMstSlvDeltaTimeStamp = Reg(UInt(32.W)) //主差从差时间差(中间变量)
val deltaFinal = Reg(UInt(32.W)); io.deltaFinal := deltaFinal //当前时间戳与主站时间差
val mstSlvDeltaTimeStamp = Reg(UInt(64.W)) //主发从接时间差(中间变量)
val deltaMstSlvDeltaTimeStamp = Reg(UInt(64.W)) //主差从差时间差(中间变量)
val deltaFinal = Reg(UInt(64.W)); io.deltaFinal := deltaFinal //当前时间戳与主站时间差
// val recoTimeStamp = Reg(UInt(64.W)) //时钟补偿寄存器
@@ -860,7 +868,12 @@ trait SlaveParserSync{ this: SlaveParserBase =>
//更新上行本地时间戳寄存器
when( upRecParser.io.frameReq.fire & upRecParser.io.frameReq.bits.frameStyle === FRAME_STYLE_COMMON ){
upTimeStamp := io.cReg.timeStamp
slvDeltaTimeStamp := io.cReg.timeStamp - downTimeStamp
// slvDeltaTimeStamp := io.cReg.timeStamp - downTimeStamp
addr64_op1 := io.cReg.timeStamp //组合逻辑
addr64_op2 := subOp2(downTimeStamp) //组合逻辑
addrConflict(0) := true.B //组合逻辑
slvDeltaTimeStamp := addr64_res //时序逻辑
}
//下行接收
@@ -898,7 +911,13 @@ trait SlaveParserSync{ this: SlaveParserBase =>
} .elsewhen( syncCnt === 7.U ){
mstTimeStamp := Cat( downRecParser.io.data.bits, mstTimeStamp(55,0) )
} .elsewhen( syncCnt === 8.U ){
mstSlvDeltaTimeStamp := mstTimeStamp - downTimeStamp
// mstSlvDeltaTimeStamp := mstTimeStamp - downTimeStamp
addr64_op1 := mstTimeStamp //组合逻辑
addr64_op2 := subOp2(downTimeStamp) //组合逻辑
addrConflict(1) := true.B //组合逻辑
mstSlvDeltaTimeStamp := addr64_res //时序逻辑
mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31, 8), downRecParser.io.data.bits )
} .elsewhen( syncCnt === 9.U ){
mstDeltaTimeStamp := Cat( mstDeltaTimeStamp(31,16), downRecParser.io.data.bits, mstDeltaTimeStamp(7,0) )
@@ -912,10 +931,19 @@ trait SlaveParserSync{ this: SlaveParserBase =>
}
when( RegNext(isSync) & ~isSync ){
val deltaMstSlvDeltaTimeStamp_org = mstDeltaTimeStamp - slvDeltaTimeStamp
deltaMstSlvDeltaTimeStamp := Cat( deltaMstSlvDeltaTimeStamp_org.extract(deltaMstSlvDeltaTimeStamp_org.getWidth-1), deltaMstSlvDeltaTimeStamp_org(deltaMstSlvDeltaTimeStamp_org.getWidth-1, 1) ) //(mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1
// deltaMstSlvDeltaTimeStamp := (mstDeltaTimeStamp - slvDeltaTimeStamp) >>> 1 //(mstDeltaTimeStamp - slvDeltaTimeStamp) >> 1
addr64_op1 := mstDeltaTimeStamp //组合逻辑
addr64_op2 := subOp2(slvDeltaTimeStamp) //组合逻辑
addrConflict(2) := true.B //组合逻辑
deltaMstSlvDeltaTimeStamp := Cat(addr64_res(63),addr64_res(63,1)) //时序逻辑
} .elsewhen( RegNext(RegNext(isSync)) & ~RegNext(isSync) ){
deltaFinal := mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
// deltaFinal := mstSlvDeltaTimeStamp + deltaMstSlvDeltaTimeStamp
addr64_op1 := mstSlvDeltaTimeStamp //组合逻辑
addr64_op2 := deltaMstSlvDeltaTimeStamp //组合逻辑
addrConflict(3) := true.B //组合逻辑
deltaFinal := addr64_res //时序逻辑
}