From c6aa7416fc6b66778bdf080f7a381ed7343a5d25 Mon Sep 17 00:00:00 2001 From: Ruige Lee Date: Wed, 13 Aug 2025 10:52:49 +0800 Subject: [PATCH] =?UTF-8?q?=E5=B0=9D=E8=AF=953=E7=9B=B8=E4=BD=8D?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main/scala/backBoard/ebus/CDRIn.scala | 12 ++++++------ src/main/scala/backBoard/shin/ShinTop.scala | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/main/scala/backBoard/ebus/CDRIn.scala b/src/main/scala/backBoard/ebus/CDRIn.scala index 625389a..90f3ffa 100644 --- a/src/main/scala/backBoard/ebus/CDRIn.scala +++ b/src/main/scala/backBoard/ebus/CDRIn.scala @@ -70,21 +70,21 @@ trait CDRInMultiSample{ this: CDRInBase => //multiCLK 需要按照滞后相位接线，即0为最先到达，1次先 - val multiCLK = IO(Input(Vec(6, Bool()))) + val multiCLK = IO(Input(Vec(3, Bool()))) - val sampleReg = Wire(Vec(9, Bool())) + val sampleReg = Wire(Vec(5, Bool())) - for( i <- 0 until 6 ) { + for( i <- 0 until 3 ) { sampleReg(i) := withClockAndReset(multiCLK(i).asClock, reset.asBool){ ShiftRegister( io.serDat, 2 ) } } - for( i <- 6 until 9 ){ - sampleReg(i) := withClockAndReset(multiCLK(i-3).asClock, reset.asBool){ RegNext(sampleReg(i-3))} + for( i <- 3 until 5 ){ + sampleReg(i) := withClockAndReset(multiCLK(i-2).asClock, reset.asBool){ RegNext(sampleReg(i-2))} } - val asyncSerDat = PopCount(sampleReg) >= 5.U + val asyncSerDat = PopCount(sampleReg) >= 3.U // sampleReg.count( (x: Bool) => (x === true.B) ) >= 12.U diff --git a/src/main/scala/backBoard/shin/ShinTop.scala b/src/main/scala/backBoard/shin/ShinTop.scala index a482e1c..cddf0f9 100644 --- a/src/main/scala/backBoard/shin/ShinTop.scala +++ b/src/main/scala/backBoard/shin/ShinTop.scala @@ -11,7 +11,7 @@ class ShinTopIO extends Bundle{ val uDatIn = Input(Bool()) val uDatOut = Output(Bool()) - val multiCLK = Input(Vec(6, Bool())) + val multiCLK = Input(Vec(3, Bool())) val iqspi = new QSPIInterfaceIO val ospi = new SSPIInterfaceIO