shin主站逻辑代码写完，没编译

src/main/scala/backBoard/shin/ShinSlv.scala

@@ -4,3 +4,60 @@ import chisel3._
 import chisel3.util._
 
 
+abstract class ShinSlvPhyBase extends Module{
+  val downStreamCdrOut = Module(new CDROut)
+  val downStreamCdrIn  = Module(new CDRIn )
+
+  val upStreamCdrOut = Module(new CDROut)
+  val upStreamCdrIn  = Module(new CDRIn )
+
+  
+
+}
+
+trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase =>
+  val downStreamFifo = Module( new Queue( new AXIS_Bundle(8), 8 ) )
+  downStreamCdrIn.io.axis <> downStreamFifo.io.enq
+  downStreamFifo.io.deq   <> downStreamCdrOut.io.axis
+}
+
+trait ShinSlvPhyUpStream{ this: ShinSlvPhyBase =>
+
+}
+
+// trait ShinSlvPhyCloseLoop{ this: ShinSlvPhyBase =>
+
+// }
+
+
+abstract class ShinSlvLinkBase extends ShinSlvPhyBase
+with ShinSlvPhyDownStream
+with ShinSlvPhyUpStream
+// with ShinSlvPhyCloseLoop
+{
+
+}
+
+trait ShinSlvLinkInit{ this: ShinSlvLinkBase =>
+
+}
+
+trait ShinSlvLinkSync{ this: ShinSlvLinkBase =>
+
+}
+
+trait ShinSlvLinkBCast{ this: ShinSlvLinkBase =>
+
+}
+
+trait ShinSlvLinkUCast{ this: ShinSlvLinkBase =>
+
+}
+
+abstract class ShinSlvBase extends ShinSlvLinkBase
+with ShinSlvLinkInit
+with ShinSlvLinkSync
+with ShinSlvLinkBCast
+with ShinSlvLinkUCast
+
+