shin主站逻辑代码写完，没编译
This commit is contained in:
RuigeLee
@@ -3,9 +3,11 @@ package BACK
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import chisel3._
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import chisel3.util._
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class Header_Info_Bundle extends Bundle{
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val length = UInt(8.W) // nlength * 16bits
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val operator = UInt(8.W)
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val length = UInt(8.W)
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val param = Vec(3, UInt(16.W))
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def init = operator === 0.U
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@@ -16,67 +18,214 @@ class Header_Info_Bundle extends Bundle{
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// class FSMC_Port_Bundle extends Bundle{
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// val ADIn = Input(UInt(16.W))
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// val ADOut = Output(UInt(16.W))
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// val ADOEn = Output(Bool())
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// val csn = Input(Bool())
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// val rdn = Input(Bool())
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// val wrn = Input(Bool())
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// val advn = Input(Bool())
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// }
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class ShinMstIO_Bundle extends Bundle{
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val FSMC = new FSMC_Port_Bundle
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val interrupt = Output(Bool())
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val testIO = Input(Bool())
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val serOut = Output(Bool())
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val serIn = Input(Bool())
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val overCLK = Input(Bool())
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}
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abstract class ShinMstPhyBase extends Module{
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val io: ShinMstIO_Bundle = IO(new ShinMstIO_Bundle)
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val mirrorDown = Module(new MirrorSRAMDP())
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val mirrorUp = Module(new MirrorSRAMDP())
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val mirrorReg = Module(new MirrorSRAMDP())
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val cdrOut = Module(new CDROut)
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val cdrIn = Module(new CDRIn )
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io.serOut := cdrOut.io.serDat
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cdrIn.io.serDat := io.serIn
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cdrIn.io.overCLK := io.overCLK
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mirrorDown.io.clockA := clock.asBool
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mirrorDown.io.clockB := clock.asBool
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mirrorUp.io.clockA := clock.asBool
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mirrorUp.io.clockB := clock.asBool
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mirrorReg.io.addrB := DontCare
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mirrorReg.io.datawB := DontCare
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mirrorReg.io.enwB := false.B
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mirrorReg.io.enrB := false.B
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}
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trait ShinMstSend{ this: ShinMstPhyBase =>
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def isSendTrig: Bool
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def isRecvEnd: Bool
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def isTimeout: Bool
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val headByte = Header_Info_Bundle.getWidth()/8
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require( headLen == 8 )
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val testIOShift = ShiftRegisters(io.testIO, headLen/2 + 1, false.B, true.B)
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val sendHeader = Reg( new Header_Info_Bundle )
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when( ~testIOShift(0) & io.testIO ){
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mirrorReg.io.addrB := 0.U
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mirrorReg.io.enrB := true.B
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} .elsewhen( ~testIOShift(1) & testIOShift(0) ){
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mirrorReg.io.addrB := 1.U
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mirrorReg.io.enrB := true.B
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sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeof(Header_Info_Bundle)
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} .elsewhen( ~testIOShift(2) & testIOShift(1) ){
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mirrorReg.io.addrB := 2.U
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mirrorReg.io.enrB := true.B
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sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeof(Header_Info_Bundle)
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} .elsewhen( ~testIOShift(3) & testIOShift(2) ){
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mirrorReg.io.addrB := 3.U
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mirrorReg.io.enrB := true.B
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sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeof(Header_Info_Bundle)
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} .elsewhen( ~testIOShift(4) & testIOShift(3) ){
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sendHeader := Cat( sendHeader.asUInt().tail(16), mirrorReg.io.datarB ).asTypeof(Header_Info_Bundle)
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}
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val isSendTrig: Bool = ~testIOShift(4) & testIOShift(3)
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val isRecvEnd: Bool
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val isTimeout: Bool
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val sendStateNext = Wire( UInt(3.W) )
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val sendStateCurr = RegNext( sendStateNext, 0.U )
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val sendHeader = Wire( new Header_Info_Bundle )
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val sendCnt = Reg(UInt(10.W))
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val sendCntNext = Wire( UInt(10.W) )
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val sendCntCurr = RegNext(sendCntNext)
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sendStateNext := Mux1H(Seq(
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(sendStateCurr === 0.U) -> Mux( isSendTrig, 1.U, 0.U ),
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(sendStateCurr === 1.U) -> Mux( cdrOut.io.axis.fire & sendCnt === ((sendHeader.getWidth()/8)*2-1).U, 2.U, 1.U ),
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(sendStateCurr === 2.U) -> Mux( cdrOut.io.axis.fire & sendCnt === (sendHeader.length << 1) - 1.U, 3.U, 2.U ),
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(sendStateCurr === 1.U) -> Mux( cdrOut.io.axis.fire & sendCntCurr === ((headByte)-1).U, 2.U, 1.U ),
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(sendStateCurr === 2.U) -> Mux( cdrOut.io.axis.fire & sendCntCurr === (sendHeader.length << 1) - 1.U, 3.U, 2.U ),
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(sendStateCurr === 3.U) -> Mux( isRecvEnd | isTimeout, 0.U, 3.U ),
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))
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when( sendStateCurr === 0.U ){
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when( sendStateNext === 1.U ) {
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sendCnt := 0.U
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}
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} .elsewhen( sendStateCurr === 1.U ){
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when( cdrOut.io.axis.fire ){
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sendCnt := Mux( sendStateNext =/= 2.U, sendCnt + 1.U, 0.U )
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}
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} .elsewhen( sendStateCurr === 2.U ){
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when( cdrOut.io.axis.fire ){
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sendCnt := Mux( sendStateNext =/= 3.U, sendCnt + 1.U, 0.U )
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}
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}
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sendCntNext := Mux1H(Seq(
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(sendStateCurr === 0.U) -> 0.U,
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(sendStateCurr === 1.U) -> Mux(cdrOut.io.axis.fire, Mux( sendStateNext =/= 2.U, sendCnt + 1.U, 0.U ), sendCntCurr),
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(sendStateCurr === 2.U) -> Mux(cdrOut.io.axis.fire, Mux( sendStateNext =/= 3.U, sendCnt + 1.U, 0.U ), sendCntCurr),
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))
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cdrOut.io.axis.valid := sendStateCurr === 1.U | sendStateCurr === 2.U
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cdrOut.io.axis.bits.tdata :=
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Mux1H(Seq(
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( sendStateCurr === 1.U ) -> sendHeader.asUInt >> (sendCnt << 3),
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( sendStateCurr === 2.U ) -> Mux( sendCnt.extract(0), mirrorDown(7,0), mirrorDown(15,8) ),
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( sendStateCurr === 1.U ) -> sendHeader.asUInt >> (sendCntCurr << 3),
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( sendStateCurr === 2.U ) -> Mux( sendCntCurr.extract(0), mirrorDown.io.datarB(7,0), mirrorDown.io.datarB(15,8) ),
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))
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cdrOut.io.axis.bits.tlast := sendStateCurr === 2.U & sendCnt === (sendHeader.length << 1) - 1.U
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cdrOut.io.axis.bits.tlast := sendStateCurr === 2.U & sendCntCurr === (sendHeader.length << 1) - 1.U
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cdrOut.io.axis.bits.tuser := false.B
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mirrorDown.io.enwB := false.B
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mirrorDown.io.datawB := 0.U
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mirrorDown.io.enrB := sendStateNext === 2.U
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mirrorDown.io.addrB := sendCntNext >> 1
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}
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trait ShinMstRecv{ this: ShinMstPhyBase =>
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def isSendTrig: Bool
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val recvStateNext = Wire( UInt(3.W) )
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val recvStateCurr = RegNext( recvStateNext, 0.U )
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val recvHeader = Reg( UInt( Header_Info_Bundle.getWidth.W) )
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val recvCnt = Reg(UInt(10.W))
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val recvLength = recvHeader.asTypeof(Header_Info_Bundle).length
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val isRecvEnd = recvStateCurr === 4.U
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io.interrupt := recvStateCurr === 4.U
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recvStateNext := Mux1h(Seq(
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(recvStateCurr === 0.U) -> Mux( isSendTrig, 1.U, 0.U ), //IDLE
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(recvStateCurr === 1.U) -> Mux( cdrIn.io.axis.fire, 2.U, 1.U ), //Arm
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(recvStateCurr === 2.U) -> Mux( cdrIn.io.axis.fire & recvCnt === ((recvHeader.getWidth()/8-1)*2).U, 3.U, 2.U ), //Header
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(recvStateCurr === 3.U) -> Mux( cdrIn.io.axis.fire & recvCnt === (recvHeader.length << 1), 4.U, 3.U ), //payload
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(recvStateCurr === 4.U) -> 0.U, //de-Arm
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))
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when( recvStateCurr === 0.U | recvStateCurr === 1.U | recvStateCurr === 4.U ){
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recvCnt := 0.U
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} .elsewhen( recvStateCurr === 2.U | recvStateCurr === 3.U ){
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when( cdrIn.io.axis.fire ){
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recvCnt := Mux( recvStateCurr === recvStateNext, recvCnt + 1.U, 0.U )
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}
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}
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when( cdrIn.io.axis.fire & ( recvStateCurr === 1.U | recvStateCurr === 2.U )) {
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recvHeader := Cat( recvHeader.tail(8), cdrIn.io.axis.bits.tdata )
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}
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val recvDataLatch = RegEnable( cdrIn.io.axis.bits.tdata, cdrIn.io.axis.fire & recvStateCurr === 3.U & recvCnt.extract(0) )
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mirrorUp.io.enrB := false.B
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mirrorUp.io.enwB := cdrIn.io.axis.fire & recvStateCurr === 3.U & ~recvCnt.extract(0)
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mirrorUp.io.datawB := Cat( cdrIn.io.axis.bits.tdata, recvDataLatch )
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mirrorUp.io.addrB := recvCnt >> 1
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val recvRamAddr = Reg(UInt(8.W))
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when( recvStateCurr === 2.U ){
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recvRamAddr := 0.U
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} .elsewhen( recvStateCurr === 3.U & recvRamAddr =/= 4.U ){
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recvRamAddr := recvRamAddr + 1.U
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}
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mirrorReg.io.addrB := recvRamAddr
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mirrorReg.io.datawB := Mux1H(Seq(
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(recvStateCurr === 3.U & recvRamAddr === 0.U) -> (recvHeader >> 16*3),
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(recvStateCurr === 3.U & recvRamAddr === 1.U) -> (recvHeader >> 16*2),
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(recvStateCurr === 3.U & recvRamAddr === 2.U) -> (recvHeader >> 16*1),
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(recvStateCurr === 3.U & recvRamAddr === 3.U) -> (recvHeader >> 16*0),
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))
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mirrorReg.io.enwB := recvStateCurr === 3.U & recvRamAddr =/= 4.U
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val ( _, isTimeout ) = Counter( range(0, 20000000), enable = recvStateCurr === 1.U | recvStateCurr === 2.U | recvStateCurr === 3.U, reset = recvStateCurr === 0.U | recvStateCurr === 4.U )
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}
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@@ -87,34 +236,40 @@ with ShinMstSend
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with ShinMstRecv
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trait ShinMstInit{ this: ShinMstLinkBase =>
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}
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trait ShinMstSync{ this: ShinMstLinkBase =>
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}
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trait ShinMstTrans{ this: ShinMstLinkBase =>
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}
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trait ShinMstError{ this: ShinMstLinkBase =>
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}
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trait ShinMstInterface{ this: ShinMstLinkBase =>
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io.FSMC.ADOEn := ~io.FSMC.rdn & ~io.FSMC.csn & io.FSMC.advn
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val latchAddr = RegEnable( io.FSMC.ADIn, ~io.FSMC.advn & ~io.FSMC.csn)
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val isAccessSRAM = ~latchAddr.extract(11)
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val isAccessReg = latchAddr.extract(11)
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val isAccessDown = ~latchAddr.extract(10)
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val activeAddr = latchAddr(9,0)
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mirrorDown.io.addrA := activeAddr
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mirrorDown.io.datawA := io.FSMC.ADIn
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mirrorDown.io.enwA := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn & isAccessDown
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mirrorDown.io.enrA := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.rdn & isAccessDown
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mirrorUp.io.addrA := activeAddr
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mirrorUp.io.datawA := io.FSMC.ADIn
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mirrorUp.io.enwA := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.wrn & ~isAccessDown
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mirrorUp.io.enrA := isAccessSRAM & ~io.FSMC.csn & ~io.FSMC.rdn & ~isAccessDown
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mirrorReg.io.addrA := activeAddr
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mirrorReg.io.datawA := io.FSMC.ADIn
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mirrorReg.io.enwA := isAccessReg & ~io.FSMC.csn & ~io.FSMC.wrn
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mirrorReg.io.enrA := isAccessReg & ~io.FSMC.csn & ~io.FSMC.rdn
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io.FSMC.ADOut := Mux( isAccessReg, mirrorReg.io.datarA, Mux( isAccessDown, mirrorDown.io.datarA, mirrorUp.io.datarA) )
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}
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class ShinMst extends ShinMstLinkBase
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with ShinMstInit
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with ShinMstSync
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with ShinMstTrans
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with ShinMstError
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with ShinMstInterface
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@@ -4,3 +4,60 @@ import chisel3._
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import chisel3.util._
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abstract class ShinSlvPhyBase extends Module{
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val downStreamCdrOut = Module(new CDROut)
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val downStreamCdrIn = Module(new CDRIn )
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val upStreamCdrOut = Module(new CDROut)
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val upStreamCdrIn = Module(new CDRIn )
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}
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trait ShinSlvPhyDownStream{ this: ShinSlvPhyBase =>
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val downStreamFifo = Module( new Queue( new AXIS_Bundle(8), 8 ) )
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downStreamCdrIn.io.axis <> downStreamFifo.io.enq
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downStreamFifo.io.deq <> downStreamCdrOut.io.axis
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}
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trait ShinSlvPhyUpStream{ this: ShinSlvPhyBase =>
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}
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// trait ShinSlvPhyCloseLoop{ this: ShinSlvPhyBase =>
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// }
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abstract class ShinSlvLinkBase extends ShinSlvPhyBase
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with ShinSlvPhyDownStream
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with ShinSlvPhyUpStream
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// with ShinSlvPhyCloseLoop
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{
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}
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trait ShinSlvLinkInit{ this: ShinSlvLinkBase =>
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}
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trait ShinSlvLinkSync{ this: ShinSlvLinkBase =>
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}
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trait ShinSlvLinkBCast{ this: ShinSlvLinkBase =>
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}
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trait ShinSlvLinkUCast{ this: ShinSlvLinkBase =>
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}
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abstract class ShinSlvBase extends ShinSlvLinkBase
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with ShinSlvLinkInit
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with ShinSlvLinkSync
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with ShinSlvLinkBCast
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with ShinSlvLinkUCast
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Reference in New Issue
Block a user