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spi读取胡乱修复，

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RuigeLee
2025-05-17 12:20:07 +08:00
parent 784bad548a
commit c4daca834c
3 changed files with 75 additions and 54 deletions
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4
src/main/scala/backBoard/shin/Interface.scala
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@@ -406,7 +406,7 @@ trait InterfaceMCUop{ this: InterfaceBase =>
))
datar := MuxCase( 0.U, Array(
((addrSel & "hFF00".U) === "h0000".U) -> RegEnable( AcquireReg(addr = addrSel), 0.U, isEnR ),
((addrSel & "hFF00".U) === "h0000".U) -> AcquireReg(addr = addrSel),
((addrSel & "hFF00".U) === "h0800".U) -> io.sram_r(0).datar,
((addrSel & "hFF00".U) === "h1000".U) -> 0.U,
((addrSel & "hFF00".U) === "h1800".U) -> io.sram_r(1).datar,
@@ -585,7 +585,7 @@ trait InterfaceLVDSop{ this: InterfaceBase =>
// io.lvds.isEnW = Output(Bool())
// io.lvds.isEnR = Output(Bool())
io.lvds.datar := RegEnable( AcquireReg(addr = io.lvds.addrSel), 0.U, io.lvds.isEnR )
io.lvds.datar := AcquireReg(addr = io.lvds.addrSel)
when( io.lvds.isEnW & isSlvMode ){